PCIe Verification Platform Based On UVM Verification Methodology

In recent years,with the rapid development of China's integrated circuit Chip field,the design of System on Chip(SoC)tends to be modular,and its complexity and process requirements are also increasing,which poses a great challenge to the verification of integrated circuits.The birth and development of Universal Verification Methodology(UVM)has greatly improved the efficiency of IC Verification.It ADAPTS to the current large-scale chip Verification by changing its own techniques.At the same time,due to the continuous update and iteration of CPU technology,its operation speed has far exceeded the bus interface speed,compared with the previous generation of PCI bus interface,PCIe bus interface has been greatly improved both from the stability of performance and from the transmission speed,so its design is bound to be more complex.Especially after PCIE 3.0,the general purpose Field Programmable Gate Array(FPGA)Verification approach has encountered a speed barrier,and UVM breaks this barrier and provides a strong support for the Verification of the PCIE bus interface design.It is also the inevitable direction of the development of high-speed bus interface verification.After an in-depth analysis of the transaction layer,data link layer and physical layer involved in the PCIE protocol,this paper presents the internal data transmission and processing mechanism of PCIE,such as 8B /10 B encoding,scramble-code,important flow control mechanism,ACK/NAK error detection mechanism,etc.On this basis,for Xilinx 7 series PCI Express V3.3 kernel,using UVM verification Methodology,using System Verilog language,through the construction of interface,transaction,sequence,scoreboard and other components.And these components are interconnected,so as to build the verification platform of PCIE bus protocol layered architecture.The verification platform can achieve the result of communicating with the real PCIE bus interface by generating the incentive and improving the relevant mechanism,and then realize the verification work of the PCIE interface design.Finally,the log information was analyzed.Data transmission was completed by naming three TLP transaction packages of Memory Write,Memory Read and Completion.At the same time,a total of nine flow control DLLP transaction packages and ACK/NAK transaction packages were generated through the normal state jump of the state machine.Realize flow control and ACK/NAK error detection mechanism,so as to ensure the normal transmission of data.In addition,the implementation of such as 8B /10 B coding,scramble code and other mechanisms,again proved that the design of the verification platform to meet the PCIE interface project verification requirements.Compared with the traditional verification methods,this platform makes full use of the relevant characteristics of UVM verification Methodology,greatly improves the scalability,reusability and portability of the verification platform,and perfectly fits the relevant requirements of the current large-scale chip verification.