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The Application Of UVM Verification Methodology In SSD Controller SoC Verification

Posted on:2016-04-11Degree:MasterType:Thesis
Country:ChinaCandidate:W N GuiFull Text:PDF
GTID:2308330503476344Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
Nowadays, with the significant increasing of the complexity and scale of SoC (System on Chip) design, the traditional verification techniques are not able to meet the requirement of the project schedule any more. And, because of the widely use of IP reuse technology, engineers always have to spend tremendous efforts on learning details inside IP design, and developing complex testbench and testcase for each IP. In face of huge pressure of verification, verification industry currently develops a new verification methodology UVM (Universal Verification Methodology), which relies on strong and proven industry foundations. It is the trend of verification technology in the future.This thesis, which is based on research on the core idea of UVM and Register Model, uses the UVM to build a testbench for SSD(Solid Stata Disk) controller SoC chip, including reusable interface UVC (UVM Verification Component), module and system UVC, and system Register Model. After analyzing the structure and functional requirement of the chip, this thesis extracts the functional points, uses the developed UVM testbench to verify the whole chip, and gives the verification results of important module and coverage analysis at last. The designed UVM testbench has high efficiency and reusability. It supports constrained random stimulus generation, automatic testing and statistic of functional coverage, which greatly improve the completeness and efficiency of verification. And the testbench can customize the required structure of testbench, integrate the related UVCs and change the condition of random test vectors at any time, which can maximize the reusability and flexibility. In addition, Register Model provides a way to tracking and accessing register contents of DUT, which can be used to monitor the chip behavior and generate higher level stimulus.The verification methods in this thesis are efficient and applicable, which could be applied to the verification of other SSD controller chips or similar chips.
Keywords/Search Tags:SoC system verification, verification methodology, UVM testbench, reusable UVC, Register Model
PDF Full Text Request
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