ESD Protection Design And Characteristics Of Advanced Process Integrated Circuits

Electrostatic discharge(ESD)is a common phenomenon in life.Studies show that 37% of integrated circuit failures each year are due to ESD / Electrical Over Stress(EOS).Especially in the Fin Field-effect-transistor(FinFET)process,where the feature size is getting smaller and smaller,ESD has an increasing impact on the reliability of integrated circuits.In order to improve the quality of electronic products,ESD protection research is necessary.Based on28 nm CMOS process and 7nm FinFET process,this paper analyzes a vulnerable chip of **company to find its weak point of ESD protection,proposes a complete ESD protection solution,and designs corresponding ESD designs under the corresponding processes.New device for windows.The dissertation studies the ESD resistance defects of diodes and GGNMOS,and establishes simulation methods of GGNMOS and diode devices.The main research contents and conclusions of this paper are as follows:1)The typical discharge model and equivalent circuit of ESD are analyzed.The waveform characteristics and failure mechanisms of different ESD discharge models were compared.The principle and usage of the Very Fast Transmission Line Pulsing(VF-TLP)and Transmission Line Pulsing(TLP)test machines used in this paper are introduced.2)Perform a failure analysis on a failed chip,determine its failure mechanism,analyze its failure reason,give improvement ideas and verify.In the 28 nm CMOS process and7 nm FinFET process,a new ESD protection device that meets the needs of the chip was designed and applied to the company’s next generation products.In the 28 nm process,a new area-efficiency diode-triggered SCR(ASCR)is proposed.The device has a trigger voltage of 1.82 V,a sustain voltage of about 1.55 V,an ESD width robustness of 48.1m A / μm,and a small device hysteresis.Strong anti-latch capability,can discharge 1.45 A ESD current under 7.2V voltage.Under the 7nm FinFET process,a new type of Modified-Diode-String-SCR(MDSSCR)is proposed.The trigger voltage is 1.8V,the failure current is 2.1A,and the robustness is as high as 5.0m A /μm2.At the same time,the device has no hysteresis,so The device’s anti-latch capability is greatly improved.The device’s parasitic capacitance is about 30 f F,which meets the low capacitance requirements of the FinFET process.3)For the 22 nm CMOS process,a new Tree-path-SCR(TPSCR)is proposed.The device has three bleed paths,which can enhance the robustness of the device.4)Study the impact of non-standard ESD pulses on the performance of ESD devices.Including: the response of GGNMOS and diode devices under different ESD pulse rise times,and the response of GGNMOS and diode devices under long pulse width conditions.This paper analyzes the turn-on hysteresis and pre-shutdown phenomenon of the Power Clamp structure used for power pin ESD protection under power-on,and designs a new power pin ESD protection circuit under power-on.5)Verilog-A was used to establish the behavioral model of the diode and GGNMOS device,and the I-V characteristic curves of these two devices were well simulated.Combined with FinFET process files,the effects of different structural parameters of diode devices on their current and voltage characteristics were simulated and analyzed.Participated in the design of the circuit simulation model of the diode.By adding a conductivity modulation module and a variable resistor to the conventional model,the transient characteristics of the diode and the self-heating phenomenon of the diode can be better simulated.