Physical Design Of Low Power MC Module Based On Samsung 11nm Process

The ever-reducing process dimension and chip area,as well as the ever-increasing power consumption density impose unprecedentedly huge challenges on today’s digital IC designers.The motion compensation module is to solve the smearing and blurring of smart TVs when displaying moving images,and to meet people’s requirements for clearer,brighter,and more shocking video images.How to reduce power consumption under the precondition of guaranteeing performance while satisfying the market’s demand for low-power and high-performance products simultaneously has become an issue of great concern among designers.The main research contents of the thesis are as follows:(1)The low-power physical implementation of MC module is fulfilled by using low-power optimization methods such as power switches and multi-threshold devicesbased on the SAMSUNG 11 nm process..Further optimization direction is proposed based on the analysis results.(2)Floorplan is adjusted.Optimize the layout of macro unit.The layout of Macro units is the basis of physical implementation.A good macro unit layout can accelerate timing convergence and reduce the area and power consumption after the physical implementation.On the basis of previous GPU projects,this paper puts forward suggestions for improvement of macro unit layout and improved macro unit layout results.(3)Automatic adjustment of clock tree structure is conducted using CCD(concurrent clock & data flow)technology.The data path and the clock path can be optimized simultaneously using CCD technology at the same time,no longer for the goal of continuously reducing the clock skew of traditional clock trees.Automatic adjustment of clock tree can be achieved by using tools according to the actual situation,and it is feasible to make full use of the front-end timing margin(useful skew)to improve timing and further reduce the threshold and the number of short-channel devices,thereby reduce power consumption.(4)The timing fix process is optimized.First,special timing violation is repaired by compiling scripts,and then ICE(Integrated Circuit Explorer)is optimized for process repair to avoid mass insertion of low-threshold,short-channel devices caused by excessive repair.Power consumption is further optimized on the precondition of ensuring timing closure.(5)The optimized process is adopted for physical implementation of MC module again.The thesis draws the following conclusions through comparison and analysis of PPA data before and after optimization: First,the static power consumption after optimization is reduced by 11.51% than that before optimization,10% greater than the target value.The total dynamic power consumption is reduced by 3.94%,3% greater than the target value.The target setting is fulfilled and the product competitiveness is improved;second,the goal of the static power consumption not higher than 15 mw and the total dynamic power consumption not higher than 600 mw is achieved;third,after all approvals are completed,SVT of the MC module is improved by 5.71%,LVT is reduced by 5.14%,ULVT is reduced by 0.57%,and the proportion of low-threshold and short-channel device usage has declined sharply,which greatly reduced power consumption loss.The ultimate low-power MC module under study in this project can meet the approval standard,which is of certain reference significance for other studies of low power consumption.