Low-Power Physical Design Of DDR PHY Module Based On 5nm Process SoC Chip

As semiconductor technology advances towards the 5nm process node,the scale of integrated circuits is getting larger and larger,with a small mobile phone chip now integrating tens of billions of transistors.In the past,IC designers mainly focused on chip performance,area,and cost.However,in recent years,with the popularity of portable electronic products,the semiconductor industry has paid more attention to the power consumption and speed of integrated circuits.Reducing power consumption is a very important goal in today’s chip design,as it can extend battery life,reduce heat dissipation issues,increase chip reliability,and lower production and operation costs.Therefore,reducing power consumption is a crucial factor to consider in today’s chip design.The research object of this paper is the SoC chip DDR PHY module based on TSMC’s 5nm process.With the help of Cadence’s Innovus layout and routing tool,the low-power physical design and power consumption optimization of the module are completed.The main work and specific achievements of the paper are as follows:(1)Completed the physical design of DDR PHY module in TSMC 5nm process SoC chip.The project relies on the 5nm technology of Taiwan Semiconductor Manufacturing Company and Cadence’s Innovus tool to complete the entire physical design process,including data preparation,layout planning,power supply planning,standard unit layout,clock tree synthesis and wiring,providing a new idea for the physical design under the 5nm technology.(2)Analyze the design principle of low power consumption.Firstly,two kinds of power consumption in IC are introduced: static power consumption and dynamic power consumption.Aiming at these two power consumption,five low power physical design schemes are proposed,which are dynamic voltage frequency adjustment,multi-power supply voltage domain,power supply turn-off technology,gated clock technology and multi-threshold voltage technology.Five low power physical design solutions were implemented in the DDR PHY module,which reduced the total power consumption of the module by 22%.(3)After the completion of the physical design,the modules are checked before delivery.Firstly,the timing sequence of the module is analyzed,and the static timing analysis method is used to analyze all the timing sequence paths in the module,so as to find out the timing sequence paths that violate the timing constraints and repair them.Secondly,the physical verification of the module includes design rule check,circuit rule check and antenna effect check.Finally,the logic equivalence of the module is checked to ensure the logic of the module is correct.The final module consisted of 59 macros and 1,563,608 standard cells,with a main clock frequency of 806 MHz,a total power consumption of 147.52 m W,and a module utilization of 67.68%.The module met the delivery standard and was ready for chip fabrication.