Design And Implementation Of RISC-V Extended Instruction Set For Network Application

With the continuous development of information technology and intelligence,chip technology has been paid more and more attention,and instruction set architecture is an indispensable part of chip technology.However,ARM and X86 instruction set architecture that dominate the market today are not It is not open source,development and design require high licensing fees and instructions are huge and complex,which seriously hinder the development of instruction set.As a completely open source and streamlined instruction set architecture,RISC-V perfectly solves the intellectual property and complexity issues of ARM and X86,greatly reduces the threshold of chip development,and attracts a large number of developers to join the research of RISC-V instruction set.Although the research on RISC-V instruction set extension is an important research direction,because the RISC-V instruction set architecture has appeared for a short time,the current research on RISC-V instruction set mainly focuses on the implementation of processor,while the research on RISC-V instruction set extension is very little.Generally,when enterprises develop custom processors,they need special instructions Make custom extension.The main research content of this paper is the design of RISC-V extended instruction set for network application.The P4 basic action and risc-v extension instruction technology of SDN are studied and analyzed respectively.The P4 basic action in SDN is mapped to RISC-V instruction set to realize one-to-one correspondence between P4 action function and RISCV extension instruction.Thus,the RISC-V instruction set architecture is creatively combined with software defined network(SDN),and a set of RISC-V extended instruction set for SDN is designed,which realizes the RISC-V extended instruction set for network application.The main research work is as follows:(1)This paper studies and analyzes the P4 programmable data plane technology and the basic actions of P4,introduces in detail the modular structure,register structure and six basic instruction formats of RISC-V instruction set architecture,and discusses the instruction set extension technologies to be used in RISC-V instruction,such as instruction code length,instruction code space,basic opcode space,green space extension and brownfield extension,so as to lay a foundation for instruction extension It has laid a solid foundation.(2)This paper studies and analyzes the instruction set design process,and on this basis,analyzes the design process of RISC-V extended instruction set,introduces in detail the RV32 I instruction set to be implemented in the extended instruction set,then analyzes the basic action of P4,designs the RISC-V extended instruction set corresponding to the action function of P4,and gives the instruction format of the extended instruction according to the basic instruction format.(3)RISC-V instruction set dedicated riscv-gnu-toolschain tool chain and riscv-tools simulation environment were built,and on this basis,riscv-gnu-toolschain tool chain and riscv-tools tools were extended to support compilation and run custom instructions.Finally,the RISC-V extended instruction set is verified and analyzed.