Design And Realization Of DSP Instruction Extended RISC-V Processor

The RISC-V instruction set architecture is a reduced instruction set architecture.Compared with other instruction set architectures that exist today,it has the characteristics of open source and free,low development difficulty,and strong scalability.In this thesis,a microprocessor core is designed based on the RISC-V instruction set and implement instruction extensions for accelerating digital signal processing applications by combining the excellent scalability of RISC-V.First,a five-level pipeline microprocessor core is implemented based on the RISC-V instruction set architecture,which implements the I,M,F,and C instruction sets of the RISC-V instruction set architecture and supports machine mode privilege.After the processor's design is completed,the pipeline of the processor is optimized into three or four variable stages,so that the processor uses less resources without reducing performance.Then,some common digital signal processing applications are analyzed,and 47 new instructions are designed to accelerate the digital signal processing applications.The processor core and the RISC-V toolchain are then modified to support all the instructions designed above.The results show that the toolchain is able to compile and disassemble the new instructions,and that the processor can execute the compiled program with correct results.Finally,based on the above hardware and software design,the design is first tested on the processor core using the official RISC-V function-oriented test set and the compliance-oriented test set.The test results show that all tests passed except for the address misalign test,which fails because the processor no longer issues an exception for16-bit aligned addresses after supporting compressed instructions.After the tests are completed,the processor is implemented in FPGA and a program is written to make the processor core send data out through the UART serial port.The general performance of the processor core is then tested,and the results show that the performance of the processor core in this thesis is higher than ARM's Cortex-M0 processor and Hummingbird E203 processor,and the static branch prediction of the processor in this thesis can reach about 70% correct rate.Finally,the performance of the extended instructions is tested,and the results show that the time required to perform the convolution operation with extended instructions at 32-bit data width is 30.9% of that without extended instructions,and the time required to perform the fast fourier transform algorithm is 60.4% of that without extended instructions and the time required to perform the convolution operation with extended instructions at 16-bit data width is 16.4% of that without extended instructions.