Research On Key Technologies Of Low-jitter Cascaded Phase-locked Loop

The past two decades have been the golden age of rapid development of mobile communications.Whether it was saying goodbye to 1G and embracing 2G in 2001,or the fact that 5G communications with low latency,low power consumption,and high reliability have gradually become popular in our country,this all benefit from the advancement of wireless radio frequency transceiver technology.Playing an extremely important role in many RF transceiver systems,the phase-locked loop frequency synthesizer can quickly adjust the oscillator quickly to generate high-frequency,high-precision local oscillator signal by the feedback system.At present,thanks to the continuous reduction of the feature size of the CMOS process,fully integrated RF transceiver chips are widely used in many wireless communication products.Accordingly,higher-performance phase-locked loop frequency synthesizers must be designed to adapt to this trend.In particular,new breakthroughs are required in terms of high output frequency,wide frequency conversion range,low power consumption,low jitter,etc.Therefore,this thesis focuses on the in-depth research on the challenges faced by the low jitter phase-locked loop frequency synthesizer in the design process and the key technologies required.The main contributions of this work are presented as follows:This thesis firstly introduces some performance indicators worthy of attention in the phaselocked loop frequency synthesizer in detail,then briefly describes the basic structure and working principle of the phase-locked loop,and constructs the linear model of the entire phase-locked loop in the S domain for further research.The dynamic characteristics and stability of the loop are analyzed,and then various noise sources are introduced on the basis of the model,the noise transmission characteristics of the loop are analyzed,and the ways to optimize the phase noise at the system design level are summarized.Secondly,starting from the design orientation,the thesis analyzes the sources of jitter and how to reduce jitter.Due to the limitations of the single-stage phase-locked loop structure,the jitter optimization to it is not effective enough especially when the output frequency is high and the total frequency division ratio is large.To solve these problems,the idea that lower jitter than the single-stage structure can be achieved by making the best of the bandwidth of each stage in cascade PLL theory is clarified in this thesis.And a cascaded PLL with dual-path phase-locked loop(DPPLL)and subsampling phase-locked loop(SSPLL)involved for ultra-low jitter is proposed in this thesis.Combining the advantages of small area and low phase noise brought by the separation of DPPLL proportional path and integral path,and the advantages of low phase noise and low power consumption brought by SSPLL due to no high-speed divider,the proposed PLL realizes the optimization of jitter without adding a huge amount of area and power consumption.Then,all loop parameters in system-level design are given.According to the design steps from the system level to the module level,then,the thesis details the working principles of the frequency and phase detector,charge pump,voltagecontrolled oscillator,frequency divider,sub-sampling phase detector,sub-sampling charge pump and other modules.Simultaneously,transistor-level design considerations have been studied and analyzed in depth,and the design of some modules has been optimized.Last but not least,the function and performance of each module and the whole loop are verified by simulation.Based on 65 nm CMOS process,this thesis designs a low-jitter cascaded phase-locked loop frequency synthesizer with an output frequency of 16.6-20.5GHz.The simulation results at27℃,1.2V power supply voltage and tt corner illustrate that the output phase noise is-111.0d Bc/Hz and-132.3d Bc/Hz for the frequency offset of 1MHz and 10 MHz of the 20 GHz carrier wave,respectively;in the integration interval of 10KHz-100 MHz,the clock jitter is 82fs.