Research On Cooperative Hardware Signature System Based On Asymmetric National Encryption

Cryptography is an important means to ensure information security,among which asymmetric ciphers can realize digital signatures,a technology that can verify the identity information of message senders,and play a key role in maintaining network security.To achieve independent control in the field of information security,China has actively participated in the independent research and development of cryptographic technology and built a set of cryptographic algorithm system with independent intellectual property rights.SM2 and SM9 algorithms as asymmetric cryptographic algorithms in domestic cryptographic algorithms,this thesis designs and implements a cooperative hardware signature system based on SM2 and SM9 asymmetric national cryptographic algorithms.The system supports the cooperative digital signature of SM2 and SM9 algorithms and has high system security while ensuring computational efficiency.In the process of designing the cooperative hardware signature system,in order to achieve higher computation speed or lower resource occupation,this thesis researches and optimizes the hardware design of the relevant algorithms of national cryptographic SM2 and SM9,and the main work is as follows:(1)To reduce the signature execution time,two parts are optimized at the level of bilinear pair operation and elliptic curve operation: for the point multiplication operation,this thesis proposes an improved scheduling hardware architecture based on the Montgomery point multiplication algorithm.The architecture is implemented based on the optimal parallelism at the point multiplication level and further reduces the computational complexity by improving the intermediate parameter computation.Combined with the proposed improved modular multiplication unit,the overall 23.17 k LUTs hardware resources are occupied and a point multiplication operation can be completed in 0.56 ms.Compared with other similar designs,the performance of the point multiplication module AT is improved by at least 100%.For the Miller operation,an efficient hardware scheduling of Miller parallel execution is proposed in this thesis by optimizing the internal point operations and the computation of linear functions.The utilization of lower-level key modular multiplication hardware resources during execution can reach more than98%,which reduces the time by 2/3 compared with the traditional serial computation.(2)For the most critical base domain modular operation at the bottom of the system,this thesis implements a parallel iterative Montgomery modulo unit through a hybrid pipelining technique and an improved modular execution process,which takes 0.432 us to complete three modular multiplication while occupying 8.17 k LUTs of resources.The hardware AT performance parameter is only 1.173,which is more than 50% better than most other research results.In addition,an efficient implementation of the extended domain modular operation involved in the SM9 algorithm is presented.The optimal execution process is designed based on the schedulable subdomain operation units using the Karatsuba idea and the modular square property.Based on the above hardware optimization design,other hardware modules are integrated to realize the final SM2 and SM9 two-party cooperative hardware signature system.The signature system supports both SM2 and SM9 co-signing algorithms and realizes the sharing of underlying computing resources.The overall design ensures system functionality and application scalability while achieving high utilization of computing resources.The system is synthesized and simulated on the XC7V690 FPGA chip on the vivado software platform,and the results of resource utilization and timing of key modules are compared with other research results to show the advantages of the design.The final analysis shows that the signature system designed in this thesis can execute 1724 times per second for SM2 two-party co-signature and 317 times per second for SM9 two-party co-signature.