Design Of Real-time Image Acquisition And Transmission System Based On FPGA

With the development of science and technology,the application of digital image acquisition and transmission has become more and more common.The traditional serialized processing method based on the software system can no longer meet these requirements,Therefore,the realization of image data acquisition and transmission by means of hardware systems has become a research hotspot.Based on this hot spot,this paper designs a real-time image gathering and transportation system based on FPGA.The proposed system uses OV5640 CMOS image sensor to capture high-resolution video data;uses Xilinx Artix7 series FPGA chip as the core controller;uses DDR3 SDRAM and combines ping-pong operation to store image data to solve the problem that the video data capacity is too large and FPGA resources are not enough to store;uses one way Gigabit Ethernet to transmit data To ensure the high speed and reliability of image data transmission in long-distance transmission;to ensure the high resolution and high reliability of image data transmission in close distance,we use one HDMI transmission.The main innovations and work of this paper are as follows:(1)The framework of the whole system is formulated,and the whole system is divided into OV5640 driver module,image storage module,clock management module,image preprocessing module,Gigabit Ethernet driver module and HDMI driver module from top to bottom.And try to parametrically design each of the sub-modules to facilitate the maintenance and modification of the code in different scenarios for subsequent applications.(2)Compared with the traditional hardware realization acquisition and transmission system,this system has added the image preprocessing module.It is convenient to reserve outgoing interfaces for subsequent more complex applications.(3)The design idea of the state machine is used to complete the configuration of the camera registers and collect the image data into the FPGA.The FIFO-IP core is used to solve the data metastability problem caused by cross clock domains during data transmission,and realizes the Data read and write storage in DDR3 SDRAM memory.(4)According to the protocol characteristics of Gigabit Ethernet and HDMI interface,using Verilog hardware description language,and adopting the idea of sub-module design and state machine design,the RTL design of the dual-channel transmission module is completed.(5)Program the entire top-level system into the FPGA and pass debugging and verification.Finally,the upper computer and the display screen with HDMI interface can transmit stable image data with a resolution of up to 1920×1080, which meets the system design requirements.