Hierarchical Physical Design Based On LDPC Encoding And Decoding Chip

With the continuous reduction of chip manufacturing process nodes,the chip integration continues to improve,and the complexity of chip design continues to increase,which brings great challenges to integrated circuit design.High frequency,low power consumption,low cost and short cycle have become competitive advantages.At the same time,the impact of advanced technology makes Timing closure more difficult and the design cycle longer,which forces designers to adopt more advanced design methods to improve design efficiency.This topic comes from a research project in the laboratory on LDPC(Low Density Parity Check)encoding and decoding.Based on the completion of the RTL(Register Transfer Level)design for LDPC encoding and decoding,this thesis completed logical synthesis and hierarchical physical design,and ultimately achieved timing and physical verification of the design,obtaining GDS(Graphic Data System)Ⅱ files that meet the design requirements.In the physical design process of the chip,the RTL code of the separated sub modules in the front-end design is first synthesized in general and physical ways,which improves the Timing closure of the top and sub modules.Adopting the bottom-up design method in hierarchical physical design,the layout and routing of two submodules are carried out first.The database of the submodules after layout and routing is assembled to the top level for timing budgeting,the timing constraint parameters in the submodules are updated,and the submodules are optimized.At the same time,the ILM(Interface Logic Model)information of the submodules is extracted for layout and routing design and optimization at the top level.Further time series and physical verification were performed on the top and submodules respectively.After meeting the requirements,the net tables of the top and submodules were merged for flattened time series analysis.The GDS Ⅱ files of the top and submodules were merged for physical verification.Finally,the GDS Ⅱ files that met the design requirements were generated,completing the entire chip design.This design realizes the physical design of the LDPC encoder and decoder chip.The overall scale of the chip is 1.2M gate circuit,working at 200 MHz Timing closure,passing the physical verification,and the overall power consumption is 97.2651 m W.At the same time,this article provides a detailed explanation of the work and related theories in each stage of physical design,analyzes the indicators and reports used to measure design,and proposes corresponding solutions to key problems encountered in design.This has certain reference significance for projects with hierarchical physical design of the same type and process.