Verification Of TCAM Memory Based On Novel UVM Verification Architecture

Content addressable memory(CAM)is a memory with big data storage space and fast retrieval and retrieval.Compared with CAM memory,TCAM memory can use mask query in retrieval,which is faster in retrieval.However,the traditional universal verification methodology(UVM)verification architecture cannot realize the complete test of TCAM internal data,which restricts its practical application.Therefore,it is urgent to study the TCAM memory verification based on the new UVM verification architecture,which has very important application value.The specific content of the paper is as follows:The first chapter mainly summarizes the current development of verification methodology and the research progress of CAM memory and TCAM memory,and prospects the future development direction;the second chapter introduces related concepts such as components,interfaces,and selection mechanisms inside UVM;The third chapter improves the classic UVM verification architecture,refines the internal level,and reuses its simulation test part,and realizes a new UVM-based hierarchical verification architecture.At the same time,the file content and usage methods within each level are introduced in detail.At the same time,it also analyzes in detail the emulation test(TB)part multiplexed in each layer,and how the pin＿agent component inside the TB layer provides clock reset and monitoring functions during emulation tests;Chapter 4 is based on the work of Chapter 3,in the general Based on the verification structure,the verification environment of TCAM memory is built.According to the retrieval function of TCAM,write reasonable input data incentives,and verify whether TCAM returns the address result with the data.For the read and write function of the bus to the TCAM,first write the bus signal with address and data information according to the bus protocol,and then send the bus signal to the TCAM,and the TCAM will write the corresponding data information in the address bits provided by the bus signal.When all the bus signals are sent,the data information is read from the written address bits one by one.Finally,compare the written and read data information.In this way,the functional verification of the entire TCAM can be completed;the fifth chapter uses the simulation tool to perform regression testing on the verification content.In the regression test,constantly change the input address and data,and change the DEPTH,DW,PW,STAGE,REPEAT＿NUM and other parameters for testing.Through the verification of TCAM modules,it is proved that using this new hierarchical verification architecture can reduce the code workload and realize the front-end verification of complex modules.