Design And Implementation Of Reusable Verification Platform For SDIO Host Controller

With the rapid development of the integrated circuit(IC)industry,the complexity of chip design continues to increase.At present,the mainstream ultra-large-scale IC design generally improves design efficiency by integrating third-party IP(Intellectual Property),but the time spent on functional verification exceeds 80% of the entire design cycle.How to achieve high-efficiency functional verification is an urgent problem to be solved.It can change the problems of low verification efficiency,poor reusability,and low degree of automation of traditional verification platforms by Using Universal Verificatoin Methodology(UVM)to build a reusable verification platform.It is efficient,reusable and complete and so on for IP verification.This topic comes from the "Large-scale FPGA Embedded CPU Core" project of the internship company.A reusable IP-level verification platform using UVM verification methodology was designed to research and improve the verification efficiency of the Secure Digital Input and Output(SDIO)controller IP based on the Advanced High performance Bus(AHB)specification in the ZYNQ series chips,and it applies to the verification of the whole chip.Reusable and efficient IC verification platform was researched.First,a Universal Verification Component(UVC)was designed according to the design document and the bus protocol,including the bus-type universal verification component AHB＿UVC and the module-type universal verification component SD＿UVC.The architecture of the SDIO controller IP-level verification platform was designed by integrating AHB＿UVC with SD＿UVC,and the execution flow of the verification platform was formulated.Then,a method of automatically generating register models was proposed,and the structure of the verification platform was optimized.The scheduling method between the sequence library and the virtual sequence library was proposed to start the test sequence to realize efficient test scene scheduling management.Aim to further improve the reusability of the verification platform and simulate the real situation of the circuit,a variable clock model and callback were proposed to optimize the verification platform.Finally,the automatic operation of chip regression test was realized,the coverage collection was completed and the reusability of the verification platform was analyzed.The simulation and verification results show that the SDIO controller verification platform of this design is tested normally,and the SDIO controller IP function is correct.In view of the reusability of the verification platform,the verification platform of the Static Random Access Memory(SRAM)controller was reconstructed by using the SDIO host controller verification platform,which reflected the system architecture of the verification platform,the general verification component UVC,interface model,and the efficiency brought by the reuse of transmission transactions.In addition,the reuse of the verification platform at the IP module level was also analyzed,which shows that the IP-level verification can save the time of building the verification platform.