Research On Retire Unit And Cache Coherency Bus System Based On RISC-V

As the strategic competition between China and the United States intensifies,high-performance chips have become a "bottleneck"technology for China.In particular,in the processor chip market,x86 and ARM instruction set chips occupy the vast majority of high,medium,and low-end processor chips.Breaking this monopoly,China urgently needs to launch instruction set chips with independent intellectual property rights.Based on its open-source and open-specification rules,the RISC-V instruction set has gradually formed a "three-part world" with the x86 and ARM instruction sets.However,China’s market in high-performance processor chips is still relatively weak,and advanced design methods and out-of-order super-scalar architecture optimization methods are urgently needed to achieve processor chip performance and indicators equivalent to today’s Intel and AMD.This thesis mainly studies the architecture design and optimization methods of high-performance super-scalar processors,and conducts research on key core issues such as the most important bus and instruction execution performance improvement.The optimization of multiple instruction concurrent out-of-order execution in superscalar processors is a key issue in improving processor performance and efficiency,as well as reducing processor power consumption.It involves core technologies such as instruction out-of-order parallel execution,instruction renaming and retirement processes,and cache coherence.This thesis focuses on these difficulties and conducts research on them one by one.Firstly,the thesis introduces the pipeline design of a four-issue superscalar processor based on the RISC-V instruction set,with the design of the instruction retirement unit as the focus.Based on Tomasulo hardware algorithm,it optimizes the Re-Order Buffer,Register Status Table,Instruction Retirement Control Logic and other modules,and build a Perl script-assisted universal design platform in the design process.At the same time,the frequent memory access caused by out-of-order multiple issue channels can cause blockage in the cache similar-buffers architecture,so corresponding optimization designs need to be made for its bus interface system.Secondly,the working principle of Cache is introduced,the hierarchical storage of hardware systems,the basic working principle of Cache,and the consistency problem and Barrier problem caused by the introduction of Cache structure and their solutions are explored.At the same time,the design ideas of AMBA bus are introduced,and the AXI bus protocol is mainly studied,and its transmission characteristics and channel structure design are summarized.Finally,on this basis,the hardware implementation of ACE protocol for cache consistency extension for AXI bus is introduced,and the transaction execution design of a variety of ACE protocol is studied,and the transaction receiving and sending modules of the consistent bus system include a consistency system composed of load&store unit,consistency interface unit,internal bus interface unit,processor interface unit,external bus interface unit,and other units.Similar to the instruction retirement unit research,the script-assisted method is also used in the design process to optimize the multi-groups of buffer and queue architecture.After testing all of the above design simulations,the calculation concluded that the overall IPC performance improvement was about 8.8%.