Functional Verification Of PCIe High Speed Bus Based On UVM

With the rapid development of China’s IC chip sector,the scale of digital chip design is increasing and the difficulty of digital chip functional verification is increasing.The introduction of Universal Verification Methodology(UVM)has improved the efficiency of digital chip functional verification.As the computing power of the digital chip increases,the speed of the bus becomes a bottleneck that limits the overall computing power of the system.In this context,the complexity of the PCIe(Peripheral Component Interconnect Express)highspeed bus system has grown tremendously.Therefore,it is crucial to investigate the functional verification of UVM-based PCIe high-speed bus systems.In this paper,UVM verification methodology is used to verify PCIe high-speed bus systems based on the engineering requirements of enterprises.The paper deeply analyses the verification requirements of PCIe high-speed bus,extracts its verification function points,designs UVM components including sequence generator,agent,driver,monitor and scoreboard from transaction layer,data link layer and physical layer respectively using Systemverilog and UVM verification methodology,and builds a PCIe highspeed bus system functional verification platform using these components.The platform was built using these components.To enhance the reusability of the platform,the reusable design of the components was carried out using a parametric approach,enabling the verification environment/components to be generated automatically according to different project configurations.To improve the speed of late convergence of functional coverage and the efficiency of verification incentive generation,the verification incentive generation design is based on genetic algorithms,and the basic genetic algorithm is improved by introducing a forbidden search strategy to enhance its global search capability.Functional verification and regression testing of the PCIe bus system were carried out using the verification platform based on the VCS software.The test results showed that by applying the verification excitation generated by the hybrid genetic algorithm combined with a small amount of directional excitation,the final functional coverage was 100%.By applying random verification excitation,the code coverage reached 96.7%,which met the verification target requirements.By comparison,it was found that the incentive generation method using hybrid genetic algorithm effectively improved the late convergence speed of functional coverage compared with the basic genetic algorithm,and the generation efficiency of verification excitation was improved by 18.3%,and compared with the traditional random generation method,its generation efficiency of verification excitation was improved by 37.5%.The reusable verification platform designed in this paper reduces the time spent on building the verification environment from 10.01%to 5.40%of the overall development time,improving the efficiency of the verification work.The platform uses the current advanced UVM verification methodology and is designed to be reusable,improving the cross-project reusability of the verification platform and verification components,and improving the traditional random excitation generation method based on hybrid genetic algorithms,in line with the current trend of large-scale functional verification of PCIe high-speed bus systems.