| With the popularization of"intelligence",smart sensors have been developed unprecedentedly,and the application scale and demand are growing in a blowout manner.Meanwhile,more strict requirements are put forward for its core component-ADC,including low power consumption,high precision,high CMRR,ease of multiplex,and various input signal.Ease of multiplexing is the basic requirement for ADC in multi-sensor systems,and IADC with periodic reset has unique advantages;PPD structure can achieve differential circuit performance with a single-ended circuit only,which is extremely suitable for low-power and high-precision ADC;zoom structure is the combination of SAR ADC andΔ-ΣADC and it has both high accuracy and high energy efficiency.Therefore,this thesis combines IADC,PPD and zoom to creatively propose an ADC for smart sensors,namely,zoom IADC based on PPD.At the system level,the zoom IADC in this thesis adopts the system architecture of"3bit SAR ADC+third-order 1bit IADC"and integrates it with the improved PPD structure.The main innovations of PPD include:First,a three-phase clock’s PDD implementation technology is proposed,which additionally introduces a phase sampling of both positive and negative input signals.As long as the circuit is matched,input common mode noise can be completely eliminated,and CMRR is improved;Second,an input complete decoupling technology is proposed,which uses two single-ended SAR ADCs to process the positive and negative input signals respectively.So that the positive and negative paths are fully decoupled.And in combination with the improvement of CMRR brought by the three-phase clock,the input of ADC is various which means both single-ended and differential signals can be processed.At the circuit level,a self-biased cascode amplifier based on inverter is proposed.To ensure that the MOSFETs work in the saturated region,the cascode use LVT devices,with their gates connected to the input,avoiding extra bias circuit and improving energy efficiency;AZ technology is used to improve its low frequency noise.Meanwhile,CDAC multiplexing is used to reduce the circuit area,and DWA technology is used to alleviate the mismatch of CDAC.The proposed zoom IADC based on PPD has completed the circuit and layout design in 55nm CMOS process,and has been taped out.The test results show that input reference noise is only 20.19μV with a±0.9V differential input in 0.378ms conversion time.This corresponds to an SNR of 89.9d B.The ADC’s CMRR is about 84d B through5Hz to 200Hz.At the quantization step of 15bit,the DNL of differential input is-0.53/+0.64LSB,and the INL is-1.12/+1.27LSB;the DNL of single-ended input is-0.47/+0.59LSB,and the INL is-1.44/+1.07LSB.The chip only consumes 1.07μA at a1V supply and Fo M_S=180.8d B,Fo M_W=15.8f J/step can be calculated. |
