Research And Design Of Low-Noise Sub-Sampling Phase-Locked Loop

With the continuous updating and iteration of communication technology,in order to meet the needs of users for high-speed data communication,improving communication transmission capacity has become an important challenge for engineers.As an important part of the transmission system,the phase-locked loop uses the negative feedback principle to adjust the output signal according to the phase relationship between the reference signal and the feedback signal to achieve the locking of the output signal frequency and phase.Therefore,how to make the output signal of the phase-locked loop more stable is the direction that researchers continue to explore.Based on the requirements of current high-speed communication systems,this thesis designs a phase-locked loop with low phase noise,low power consumption and high quality factor.This design uses a sub-sampling phase-locked loop architecture to effectively solve the phase-locked loop in-band noise amplification problem and achieve low output phase noise.The architecture consists of a sub-sampling loop,an auxiliary frequency-locked loop and a feed-forward noise cancellation module.The sub-sampling loop consists of a sub-sampling discriminator,a narrow pulse generator,a sub-sampling charge pump,a loop filter and a ring voltage controlled oscillator.This thesis proposes a new RC-based voltage controlled narrow pulse generation circuit with a first order RC filter and voltage controlled delay unit in the delay path to avoid the effect of sampling noise on the sampling signal,and an external control voltage to adjust the pulse width to reduce the locking time of the phase locked loop.The auxiliary frequency-locked loop consists of a frequency and phase discriminator,charge pump,dead zone generator,loop filter and voltage-controlled oscillator.This thesis uses a new dead zone generator with an adjustable dead zone range to eliminate the disadvantages of traditional dead zone generators with a large dead zone range resulting in long lock times.The output phase noise of the lock-in loop is further improved using a feed-forward noise cancellation technique,achieved by a single-ended output operational amplifier and an adjustable-gain voltage-controlled delay unit,which eliminates phase noise due to jitter in the voltagecontrolled oscillator.Matlab scientific computing software is used in conjunction with mathematical derivations to complete the analysis of the stability of the sub-sampling phaselocked loop and the solution of the loop design parameters.Cadence EDA design software is used to design the overall circuit schematic and layout,and Spectre and Hspice simulation software are used to simulate the performance of the sub-sampling phase-locked loop.After the layout has been drawn,the layout is checked for errors using the Mentor Calibre tool for DRC and LVS.This sub-sampling phase-locked loop design uses a 65 nm CMOS process.The operating voltage of the phase-locked loop is 1.8V.Under typical conditions,the sub-sampling phaselocked loop is simulated.When the output frequency is equal to 2.4 GHz,the locking time is4.49 μs,the overall power consumption is 9.295 m W,the reference spur is-44.64 d Bc/Hz,the phase noise is-120.46 d Bc/Hz at 1 MHz frequency offset,the RMS is 0.63 ps,and the quality factor FOM is-234.33 d B.The PLL performs well in power consumption,phase noise and RMS.