Design And Implementation Of Stacked SRAM With Adaptive Retention Voltage

The demand for portable,intelligent,and long battery-life products is increasing with the popularity of Io T(Internet of things)devices,making low-power design of microcontroller Unit(MCU)raise great interest among researchers.In practical applications,the standby state of Io T chips tends to occupy most of the time during a period.Thus,as one of the important sources of static power consumption in a single chip,Static Random Access Memory(SRAM),has become a significant point when it comes to power optimization.Although several techniques have been proposed to reduce SRAM leakage power,lowering its supply voltage is the most effective method.Since the outer system may have the necessity to hold its internal data,the supply voltage of SRAM in sleep mode must be greater than its minimum data retention voltage(DRV).However,the advanced technology nodes lead to the leakage improvement of traditional voltage regulation scheme not effective enough to satisfy those requirements.Under these circumstances,the idea of voltage stacking provides another solution to address such problem,based on which this paper proposes an array-stacked SRAM,enabling memory cells to hold their data under a certain voltage,roughly half of the supply voltage,when SRAM enters sleep mode.Without the need for extra voltage regulation modules,the logic components of the proposed SRAM can be turned off while the array’s voltage is maintained.Compared with previous voltage-clamping structure,this thesis analyzes the applicability of voltage-stacking scheme through several calculations and realizes voltagestacking structure on SRAM cells,enabling the stacked net to establish a stable state at half of the supply voltage.In the meantime,with the assistance of stacking-arbiter circuit,the proposed SRAM can retain its data under any given temperature where it can switch to voltage-clamping mode in low-temperature applications to achieve high data retention yield.Thus,a modeswitching circuit is proposed so that the system can flexibly configure the working state of its memory.In this thesis,an array-stacked SRAM whose capacity is 32 KB has been fabricated on22 nm.The proposed SRAM supports normal mode,shutdown mode,voltage-stacking mode,and voltage-clamping mode.The simulation results show that when the supply voltage is0.6V/0.8V and the outer system enters sleep mode,the proposed SRAM will switch to voltageclamping mode if the temperature is below 0℃.the leakage power consumption of the arraystacked SRAM at TT 25℃,FFG 85℃ and SSG 0℃ is reduced by 70%,60%,70% compared with the traditional clamping;5% leakage reduction at SSG-40℃.For SRAM in shutdown mode,the proposed design can achieve 90%,80%,90% leakage reduction.