PCI Express And Rapid IO High-speed Interconnection Technology Verification Base On FPGA

The development of integrated circuit gradually inclines to high speed and low power consumption. Since the 1990 s, the rate of the processors grows at an exponential rate, while the development of system bus and chip interconnection technique technology is stagnating. Traditional PCI bus has already failed to satisfy the high speed CPU’s demand for speed of data reading and writing, and because of the defects come from its old bus structure, it has been unable to adapt to the requirement of system architecture. Therefore, new interconnection technique is grabbing more and more attention.As a substitute for PCI bus, PCI Express bus provides the up to 256 GT/S transfer rate with the trait of high efficiency for large pieces of data transmission, simple system topology, low threshold for technology, low cost for use and design while compatible with PCI bus at the same time. PCI Express bus uses the latest high-speed serial transceiver and effective ACK/NAK protocol to guarantee the credibility of data link. Also, in the process of data sending, it transmits data in packets in order to ensuring the high efficiency of data sending and to wipe the sideband signal at the same time. Nowadays, PCI Express bus has been widely applied to the local IO bus in the computer. As a new product, Rapid IO has been widely used in the embedded system. Its maximum transmission rate can reach 25 GT/S in the case of using only four channels.Also, it has the advantage of higher efficiency in the serial bus packet transmission, more flexible topology structures and more diverse processing components, better system stability, higher efficiency of flow control mechanism, more levels of service quality and stronger error management mechanism. So it is suitable for the high real-time and reliable design of embedded system.This paper, setting foot on high-speed interconnection technique, introduces the scheme of the realization of the high-speed Internet technology of the physical layer, including high-speed difference level standards like LVDS, CML, ECL and high-speed serial transceivers using the technology such as clock recovery circuit and 8B/10 B CODEC. Also, based on the protocol and working principle of PCI Express and Rapid IO, it respectively analyzes their advantages and disadvantages and introduces their working mechanism and foundation of realization. In addition, on the basis of understanding the agreement and working principle, the paper designs an effective as well as reliable hardware test plan and a FPGA test procedures, including the design of IP core and application layer provided by Altera. Finally, it achieves the function of high-speed DMA reading and writing data between PC and FPGA development board and data transmission through Rapid IO passage between FPGA development board and DSP chip according to the design of the hardware test on the hardware testing platform of the FPGA development board.