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Development Of High-speed And Largecapicity Storage Card Based On EMMC

Posted on:2016-01-28Degree:MasterType:Thesis
Country:ChinaCandidate:B W LiuFull Text:PDF
GTID:2308330479491017Subject:Instrumentation engineering
Abstract/Summary:PDF Full Text Request
With the development of auto matic test system, the data recorder, which plays a very important part in the system, needs a higher performance storage media. e MMC is a new kind of storage that contains a flash management controller inside. e MMC is widely used in smart phones and tablet PCs due to its characters of large capicity, low cost, small size and high speed. It has obvious advantages over traditional Nand Flash devices. This paper focuses on developing a high-speed and large-capicity card based on e MMC 5.0 device. The paper proposes a new solution for updating the storage media in data recorder.The research on e MMC 5.0 specification is the base of the design. The paper introduces the main work mode, speed mode and operation timings, then summarizes the key bus protocal for the design. In hardware design, this paper introduces the technical specifications and the overall design scheme is proposed. Module design method is used in hardware design. It is consist of storage module, cache module, information record module, master controller and a PXI Express interface for extended use. The master controller is a Xilinx’s Virtex-5 FPGA of high performances in timing and I/Os. And in placement of key devices and routing of key signals of the PCB design, principles as signal direction and signal length etc, are considered.In firmware design, a detail overall logic design is proposed. The core function of the logic is realization of controlling e MMC 5.0 devices. It mainly contains command sending function module, response receiving functio n module, data writing and reading function module and the flow controlling module. The e MMC controlling logic is used to realize data transfer in HS200 mode and 8 bits bus width. In division of logic module design and interface function, some modules are resused to save FPGA’s logic resources. By timing design of the physical layer interface control logic, the versatility and portability demand for e MMC controlling logic is achieved. Cache control logic and information recording control logic are included to complete the whole storage function of the entire system.In debugging and testing, the whole system function is realized in the order of bottom module to top module. This paper mainly introduces the e MMC control logic debugging. After testing and verifying, the card storage capicity can reach up to 116 GB, and the data transfer speed of a single e MMC is above 40MB/s. The data transfer speed of the whole storage card can reach up to 150MB/s. The card function has good portability and versatility, and the design requirements are met.
Keywords/Search Tags:eMMC 5.0, FPGA, High speed and large capicity, HS200 mode, Universality
PDF Full Text Request
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