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A Low, Drop-out Regulator

Posted on:2009-07-12Degree:MasterType:Thesis
Country:ChinaCandidate:L ChenFull Text:PDF
GTID:2192360245961162Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
According to the development of consumer electronics, power management is necessary to reduce the standby power of portable applications such as cellular phones and PDAs. Voltage regulator is one of the most popular power converters widely used in power management, because of its low-noise, high precision and few off-chip components.When the voltage regulator is used widely and the fabrication technology of integrated circuit advanced, the voltage regulator with high performance is needed: Less supply voltage, less standby current, more precise out-put voltage and low different voltage between in-put and out-put voltage. So low drop-out regulator (LDO) appears. For different applications, new structures LDOs are needed.A new LDO suitable for large load capacitor is designed.Firstly, LDO is analyzed with the frequency compensation theory of amplifier. Some common structure LDOs are analyzed and find those are not suitable for driving large load capacitor.Secondly, a new structure LDO with slew-rate compensation is designed which can drive large load capacitor, using the new amplifier frequency compensation (damping-factor-control).A circuit making zero is used to solve the problem of zero and pole and improves the performance of LDO. The cascode structure improves the Power Supply Rejection Ratio.At last, a high precise reference and bias circuit are designed.Simulation results show the new LDO has low line regulation and low load regulation. In the worst case, when driving a large load capacitor, the low frequency loop gain of LDO is 108dB , the unity-gain frequency is 9.8khz, the variation of out-put voltage is less 15mv, the recovery time is 0.6us, the low frequency PSR is -60dB.the reference has a temperature coefficient(TC) of 6.9ppm/℃over the temperature range of -40 to 85℃and a line regulation (LR)of 10.6ppm/V for a supply voltage of 3.0 to 3.6V. Finally, according to the mixed-signal system layout strategy, the layout of these circuits is designed and checked, with TSMC 0.25μm 2P4M mixed-signal CMOS process.
Keywords/Search Tags:voltage regulator, LDO, damping-factor-control frequency compensation, slew-rate compensation, reference, large load capacitor, cascade, PSRR
PDF Full Text Request
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