Research Of The Charge Collection And Propagation Mechanisms Of Single Event Transients In Micro/Nano Devices

Many researches on anomalies phenomena of spacecraft showed that single event effect(SEE)is one of the main radiation effects that induced satellite failure in the space environment.With the continuous scale down of the semiconductor process size,the error caused by SETs has gradually become the dominant factor in the total soft errors in micro/nano devices.The research of the charge collection and propagation mechanisms of SETs,the failures caused by the propagation of SETs in circuits of micro/nano devices,and its internal mechanisms can provide data reference and theoretical basis for the designer to hardening chips.In this thesis,we focus on the mechanism of charge collection and propagation of the SETs effect of micro/nano devices,and a probe test platform for collecting weak SETs signals for die chips was built.In this work,a combination logic device was designed based on the 130 nm bulk silicon process and a sequential logic device was designed based on 130 nm SOI process.The mechanism of charge collection in the bulk silicon and SOI process MOSFET and the propagation characteristics of SETs in bulk silicon combinational logic circuits are studied.The propagation of SETs in the circuit may cause errors in subsequent circuits,for example,SEU may occur when a SET was captured by the sequential logic unit in the circuit.The SEU characteristics of bulk silicon and SOI sequential logic circuit were also researched.Pulsed laser,heavy-ion,and simulation are used in this work.The dissertation has carried out a detailed study from three key inspects,including the generation,the propagation,and the impaction on subsequent circuits of SETs.The main contents and achievements of this work are as follow,(1)Based on the pulsed laser single event effect test system and semiconductor probe test component,a probe test platform for collecting weak SET signals of a bare chip is built.The minimum pulse width that can be captured by the probe test platform is about 100 ps which was verified by 180 nm silicon MOSFETs.Several experiments have been carried out by this platform.(2)The SETs characteristics of 180 nm bulk silicon MOSFETs impacted by laser energy,bias voltage,gate size,and irradiation position are experimental studied use probe test platform.And the influence of heavy-ion LET,irradiation position and gate size on the SET current pulse of 130 nm SOI MOSFETs was simulated using TCAD.Research results show that 1)The increase of heavy-ion LET and bias voltage will improve the ability of charge collection in MOSFET,that 2)in silicon devices,the increase of gate length will increase the amplitude and narrow the pulse width of SETs,and the increase of gate width will increase the pulse width of SET but make a little influence on the amplitude,that 3)in SOI devices,with the increase of gate length,the SET pulse amplitude,pulse width,and the magnification of parasitic BJT decreases,and with the increase of gate width,the SET pulse amplitude and the magnification of parasitic BJT decreases,while the pulse width narrows,that 4)for T-gate NMOS,there are two sensitive positions on the drain-body junction,one of which generates the largest SETs,and another one collects the most charge.(3)The generation and propagation characteristics of SETs voltage pulse in the inverter chain are studied by injecting the SET current pulse generated by 180 nm silicon MOSFET in the experiment to the inverter chain by Hspice simulation.Additionally,the distribution characteristics of SET pulse width in 130 nm bulk silicon combinational logic circuit are studied by using pulse laser and heavy ion irradiation.The simulation results show that when the SET voltage pulse amplitude generated by the SET current pulse is large,the pulse width of SET voltage first widens and then narrows in the propagation process,and finally tends to be stable.When the SET voltage pulse amplitude is small,the SET pulse width narrows in the propagation process until it disappears.The experimental results of 130 nm bulk silicon inverter chain show that there are two(multi)peaks in SET pulse width distribution.The main reason for the double(multi)peak distribution of the SET pulse width is due to the parasitic bipolar effect and charge sharing effect of PMOS.In addition,the decrease of PMOS gate width in the inverter chain will widen the average SET pulse width.(4)The SEU sensitivity of 65 nm bulk silicon sequential logic device DFF chain impacted by supply voltage,clock frequency,circuit structure,data mode and layout structure is studied by the pulsed laser.The research shows that 1)the sensitivity of the DFF chain increases as the voltage decreases,that 2)the effect of frequency on the SEU sensitivity of the DFF chain is mainly affected by the SET pulses generated in the combination circuit combinational,that 3)the DFF chain is more sensitive to SEU during the data "0" test than the data "1" test,that 4)the SEU sensitivity of the DFF chain can be mitigated by increasing the spacing between sensitive nodes and using guard rings and guard drain.Hspice results show that the SETs pulse generated in the combinational logic celements introduced by the Set-and Reset-structure will make them more sensitive to SEU in the data "0" and "1" tests,respectively.(5)Based on the 130 nm SOI process,a DFF-chain chip with a different layout,gate size,and circuit architecture was designed,and its SEU sensitivity was studied by heavy-ion and the pulsed laser.The experimental results show that 1)the layout of DFF unit has little effect on the SEU threshold,however the SEU cross-section of DFF chain with two rows interleaved layout is lower,that 2)the SEU threshold of the DFF chain can be increased with the increase of gate length and gate width,that 3)the SEU threshold of DICE DFF chain is significantly higher than that of conventional DFF chain.In summary,the charge collection of SETs pulse generated by a transistor under the different designs is researched firstly.Based on research result,the propagation characteristics of SETs in combinational logic are studied,and the SEU effect caused by the propagation of SETs pulse in combinational logic is further studied.