Research On Single Event Effect Of 28nm FDSOI For Logic Gate

The rapid development of aerospace industry needs higher performance Aerospace integrated circuits.To improve the performance of integrated circuits by reducing the characteristic size of device the critical charge of devices,leading to the problem of Single Event Effect becoming more and more serious.Therefore,FDSOI devices are getting more and more attention with its unique anti radiation ability.The research on Single Event Effect of single transistor ignores the influence of voltage coupling on Single Event Effect.Therefore,it is of great significance to carry out Single Event Effect simulation research according to the actual circuit structure.Based on the 28 nm FDSOI process,the Single Event Effect of logic gate is studied in this paper1.Based on the tool and simulation method of Cogenda,the inverter model was established,and the Single Event Effect simulation of the inverter was carried out.The effects of the LET value,the incident position of the inverter,the load size and the size of the inverter on the Single Event Transient were studied.The research shows that the Single Event Transient of the inverter is mainly affected by the electric field intensity of the collected charge.The more effective charge collected by the electrode,the more obvious the Single Event Transient is,because the light-doped leakage region has the strongest electric field intensity,so it is the sensitive location of the Single Event Transient.When the LET value is small,the high-load inverter is not sensitive to the Single Event Transient,but when the LET value is large,the Single Event Transient duration of the high-load inverter increases and the recovery is slow.The larger the size of the inverter,the stronger the driving ability and the stronger the radiation resistance.Then two input and three input and NAND gate models are established to simulate the Single Event Effect under different input states.Through simulation,it is obtained that the sensitivity state of two input and NAND gate is10 state,and the sensitivity state of three input NAND gate is 110 state.Therefore,it is concluded that for multi-input and NAND gate,when the NMOS transistor connected with the output node is closed,and other series NMOS transistor are turned on,it is the sensitive state of Single Event Transient.By comparing the Single Event Transient between the inverter and the NAND gate,it is found that the minimum size inverter and the two input and NAND gate are relatively sensitive to the Single Event Transient,so it is necessary to carry out radiation hardening.2.An injection current source model based on Gaussian function is constructed by curve fitting for the Single Event Transient current obtained from the phase inverter and NAND gate device level simulation.The current source model in the form of Gaussian function is a model considering voltage coupling,which can be applied to both the phase inverter and NAND gate by changing parameters.Compared with the traditional dual exponential model,the current source model using Gaussian function can better match the simulation results of the device,and has better fitting results in terms of shape and pulse width.The maximum peak error is 4.9%,the maximum pulse width error is 8.5%,and the maximum half width error is 7.2%.3.Based on the simulation results of the first part,the radiation hardening of the minimum size inverter and two input and NAND gate is studied.Mainly through two ways to harden the circuit,the first way is the combination of FDSOI device features,applying back gate modulation adjustment device using the principle of threshold voltage boost circuit radiation resistance,impose negative voltage on the PMOS transistor circuit back grid bias,lower threshold,the way of increase current boost circuit of Single Event Transient recovery ability,reduce the Single Event Transient pulse width.The second radiation hardening method is carried out at the transistor-level.By adding redundant transistors,the potential difference between the two ends of the circuit sensitive transistors is reduced,and the electric field intensity is reduced,so as to reduce the amount of charge collected through drift movement,and thus to enhance the ability to resist radiation.The current source model was injected into the SPICE mesh to simulate the single particle effect.The simulation results show that the anti-radiation ability of the circuit is improved to some extent by applying the back gate bias.The radiation-resistant ability of the circuit has been improved obviously by means of transistor-level radiation hardening,and radiation hardening effect is better than that of the previous method.Finally,a 50 stage inverter chain is established to study the propagation characteristics of Single Event Transient.The simulation results show that the Single Event Transient are broadened in the later stage of the incident node,but show a trend of decreasing step by step,and finally electrical masking occurs.