Study Of Single Event Effects On Nanoscale Memory Device And Combinational Logic Device

The rapid development of aerospace technology has created an urgent need for high-performance integrated circuits.To improve the performance of integrated circuits,there are mainly two types of technical routes.One type is to continue Moore’s Law by scaling the feature size of transistors.The other type is to employ emerging three-dimensional（3D）stack integration technology.However,the scaling of transistor feature size lowers operating voltage and node capacitance,resulting in a reduction in critical charge for the occurrence of single event effects.And the reduction of sensitive node spacing makes charge sharing effect more significant.Compared with conventional planar devices,the sensitive volumes of 3D devices are distributed in each layer.Radiation effects of different layers may have a significant difference.These factors have the potential to further complicate the radiation response of advanced process devices.Therefore,the study on the mechanism of radiation effects for high-performance devices is very important for the development and performance evaluation of radiation-hardened devices.In this paper,a 90 nm bulk 3D SRAM with a two-die stack structure,a 22 nm FDSOI circuit used to characterize transient pulses,and a 65 nm bulk radiation-hardened SRAM were used to conduct ground-based accelerator simulation experiments,respectively.In addition,the ionization track profiles of heavy ions were calculated by the GEANT4 toolkit.And the radiation responses of circuit induced by heavy ions were studied by the SPICE simulation.Based on the simulation,the experimental results were further analyzed and discussed.The main results obtained are as follows:（1）The direct ionization and indirect ionization mechanisms of protons induce a significant difference in single event upset（SEU）cross sections on different layers of the 3D SRAM.The protons of 5.5 Me V induce SEUs in lower die mainly by the direct ionization mechanism,due to its highest LET value in the active region of the lower die.In other cases,protons induce SEUs by the indirect ionization mechanism of secondary particles produced by nuclear reactions.The SEU cross section of direct ionization is about 2～3 magnitude order larger than that of indirect ionization.（2）The species,range,and LET of heavy ions all have a significant influence on SEU cross sections of the 3D SRAM.At a similar LET value,the SEU cross section induced by high-energy heavy ions is about 3 times higher than that of medium-energy heavy ions.This is attributed to the wider distribution of ionization charges induced by the high-energy heavy ions.Furthermore,the range of heavy ions determines the number of layers affected by SEUs.The total SEU cross sections show a sudden decrease when the ion range is insufficient to reach the lower die.This indicates that the influence of ion species,range,and LET must be taken into account for conducting radiation effect studies and evaluations on nanoscale 3D devices.（3）The pulse quenching effect in nanoscale devices has a significant impact on the generation and propagation of single event transients（SETs）.Compared with ⁸⁴Kr ions,the pulse widths of SETs induced by ¹⁸¹Ta ions with a higher LET value are narrower.However,the GEANT4 simulation results show that the ionization charge concentration and track radius of ¹⁸¹Ta ions are larger than those of ⁸⁴Kr ions,indicating that ¹⁸¹Ta ions could cause a serious charge sharing effect.The influence of charge sharing effect on SET pulse width was investigated based on circuit-level pulse injection simulation.The simulation results show that charge sharing effect could cause pulse quenching effect,resulting in a significant reduction of the SET pulse width.（4）Dual DICE interleaving layout and EDAC code could significantly improve the radiation resistance of nanoscale devices.The hardening effect of dual DICE interleaving layout depends on the minimum spacing of sensitive node pairs in layout.The sufficient isolation of sensitive node pairs is thus required to maximize the benefit of dual DICE interleaving design.The hardening effect of EDAC code is related to the multiple bit upsets（MBUs）in a byte.For heavy ion tests with a high LET value,the benefit of EDAC code is greatly reduced because the MBU proportion in SEU increases remarkably.The dual DICE interleaving layout and EDAC code mitigate the occurrence of SEUs at cell-level and circuit-level,respectively.Combining these two hardening techniques allows devices to achieve a superior radiation resistance.This paper presents the experimental results of single event effects in a 3D SRAM and a transient pulse characterization circuit,and discusses the physical mechanisms of radiation response.Moreover,the effectiveness of radiation hardening techniques in a nanoscale device is also characterized.Based on the experimental and simulation results,the failure mechanisms of the radiation hardening techniques are discussed,and then some suggestions are given to further improve the radiation resistance of devices.These results provide necessary data and guidance for the radiation hardening design in advanced process devices.