Circuit Level Radiation Hardening By Design Method Of CMOS Digital Circuits

As we enter the 21st century, the probability of a single event (including single event upset and single event transient) continues to increase in storage circuits, sequential elements, and combinational circuits. In fact,the single event problem is already an important measure of circuit reliability issues for the IC industry. The soft error caused by the single event is an important reason for the failure of the spacecraft and is an important challenge affecting the reliability of the IC. So, how to design an effective radiation hardened integrated circuit are becoming increasingly important. In general,the radiation hardening techniques can be applied at various levels; therefore,they can be classified as system level, device/process level and circuit level mitigatio. To improve the radiation hardening ability of the IC as the starting point, this paper conducts a thorough research on circuit level radiation hardening techniques for the soft error in the IC.Based on the analysis of the single effect mechanism, the effect of single effect on the integrated circuit and the modeling of single effect, this paper summarizes a variety of the common circuit level radiation hardening techniques. This paper reviews some of the classic SEU/SET soft error tolerance hardened latches, and in view of the issue of the existing hardened latches, and finally this paper proposes a low power soft error tolerant latch(LPSET).The LPSET latch construct time redundancy circuit in the latch, not only can efficiently mask the input Single Event Transient (SET) propagated from combinational logic,and can fully tolerate the Single Event Upset (SEU) when particles strike on internal nodes, can improve the anti-radiation ability of IC. Its output node will not enter a high impedance state when a particle strikes on internal nodes, so the LPSET latch can be applied to clock-gating circuits. Based on SMIC 40nm CMOS technology library, the fault injection simulation was carried out using HSPICE simulation software.The simulations show that the LPSET latch can fully tolerate the SEU in the latch and can filter the SET propagated from the combinatorial logic. Compared with other soft error tolerant latches, the LPSET latch introduces 13.4% delay overhead on average.While it can achieve 44.3% increase in filterable SET pulse width, 48.5% reduction in power, 46.0% reduction in Power Delay Product (PDP) and 9.1 % reduction in transistor numbers on average. The LPSET latch has good soft error tolerance ability, and have lower power consumption It's helpful for improving the reliability of the integrated circuit and relieving soft error of digital integrated circuits in nanometer technologies.