Radiation Hardening Standard Cell Library Design And Implementation For A SerDes Circuit

With the development of aerospace technology,more and more complex and largescale integrated circuits are used in aerospace equipment.Integrated circuits used in the aerospace field need to have a certain resistance to radiation,so as to ensure that the spacecraft can work normally in orbit for a long time.These complex and large-scale integrated circuits need to be designed using semi-custom methods,but due to the high cost of development and maintenance of special anti-radiation process lines,using commercial process lines to achieve this purpose through special design methods is also a feasible method.Using commercial process lines to produce radiation-resistant integrated circuits need to design and implement a standard library of radiation-resistant cells.In this thesis,the basic theory of radiation effect is analyzed,and the principle and method of anti-radiation for common integrated circuits are introduced.The TID and SEE that can be hardened by design are hardened by using surrounding-gate and ”Delay-C element” structure respectively.The double exponential current source is used to simulate single event transient effect,and the resistance to single event effect is verified by simulation.A computer script for checking the consistency of the layout vs.schematic of standard cells and extraction of parasitic parameter netlist is designed and implemented,which quickly completes the physical validation of standard cells.The composition and basic principle of standard cell library are analyzed.The principle of timing measurement and the specific method of layout abstraction are introduced.Finally,a set of standard cell library is generated by automated computer script and EDA software.A 8b/10 b SerDes codec circuit is re-synthesized and physically implemented using the standard cell library designed in this thesis.The algorithm is designed and the computer program is written to complete the conversion from CDL netlist to synthesizable Verilog code,and the simulation verification is carried out using the analog mixed signal simulation technology.The specific requirements of logic synthesis and physical implementation for standard cells are deeply analyzed,and a unified simulation verification platform is designed.The simulation results show that the standard cell library can be used in ASIC semi-custom design process.Using the standard cell library,the GDS II file of the 8b/10 b SerDes codec circuit is obtained,and the netlist with parasitic parameters is extracted for SPICE simulation to verify the correctness of the standard cell library.