Research On The Circuit Structure And Radiation-Hardened Design Of Linear Regulator

Linear regulators are designed to transform noisy power voltage to stable,accurate and load irrelated voltage,of which low temperature coefficient and fast transient response are the most important technique specs.However,if under radiation,Single Event Transient(SET)effect would cause great threat to the stability of linear regulators.This thesis focuses on SET effect of the linear regulator,demonstrating its basic structure,working principle and main performance specs,and take a full analysis on its SET sensitivity and working principle.Then experiments and researches on the simulation results comparison are carried out based on one 130 nm bulk CMOS technology analog linear regulator.In the heavy ion experiment we acquire the waves caused by bombarding the most sensitive node of circuit,and fit them with results of circuit simulation,accompanied with circuit theoretical analysis and empirical data of double exponential current source,finally find out the location of the most sensitive node and parameters of double exponential current source,make it able to analyze different working points' effect on SET.This method is very accurate and effective.Simulation analysis concludes that input voltage mainly influences the amplitude of fluctuations in the output and that the load current,load capacitor mainly affect the duration of the fluctuations.Based on the analysis above,a cap-less radiation-hardened analog linear regulator was designed with optimization of temperature coefficient and transient response.Following the octagon principle of analog design,this design achieves its goal by sacrificing power.Simulation results show.that this design achieves the temperature coefficient of 15 ppm/ ?,start-up time of 1.5 us and transient fluctuation less than 100 mV with a 1 nF load capacitor(load transient of 100 nA to 100 mA within 10 ns).With various techniques like increasing capacitance in the sensitive node and increasing bandwidth of the output stage,this design achieve positive SET less than 200 mV and negative SET less than 100 mV in the simulation,which would not cause much influence in the common load circuits.Afterwards digital SET hardened linear regulators are researched to resolve the drawbacks of analog linear regulator's sensitivity on SET effect,which has not been found in the internet yet.This thesis demonstrates a 1 MHz,16 bits digital linear regulator based on classic structure and finishes the theoretical and simulation analysis.The analysis of results indicates that in order to achieve better performance,smaller output precision and more bits of shift registers should be designed.Then on this design,theoretical analysis of SET effect is done and verified by simulation.The results show that digital linear regulator is less SET-sensitive than analog linear regulator.So it is safe to adopt it to achieve radiation-hardened design in the engineering.Lastly,influence of different design specs of digital linear regulator on its SET effect is analyzed,with conclusion that under the restriction of area,power and load specs,increasing the bits as well as the clock rates can lessen the influence of SET effect.These conclusions are of high value to design better-performance regulators in the future.