The Design And Implementation Of Receiver's Circuit In SDH Network Analyzer

In optical telecommunication industry, SDH backbone network, which is in accordance with ITUT standard, will always be the core network in metropolitan area network and long-distance network. And SDH backbone network will develop persistently into a larger scale with the development of MSTP, which stands for multi-service transmitting platform. So the need of SDH network analyzer will increase constantly with the increase of SDH network. Although the domestic research, development and production of SDH have become mature, differences and special characters still exist between SDH analyzer instruments and SDH equipment. SDH instrument has special requirements of high performance, specialization, integration and modularization, so research and development on key technologies of domestic SDH instruments are urgently needed. Receiver circuit of SDH network analyzer is designed and realized in this paper based on standards related to SDH network analyzers. The receiver circuit combines with transmitter circuit, other hardware circuits and CPU etc., constituting a SDH network analyzer. And after the addition of other service interface, the analyzer can be used as a part of MSTP test instrument.ITU-T.707, ITU-T G.704 and other standards related to SDH and PDH are introduced, including frame structure, multiplexing structure, pointer features and overhead bytes of SDH as well as E1 and DS1 signal etc. of PDH, and the overall design of SDH network analyzer is presented.Design structure of receiver circuit in SDH network analyzer is confirmed. Then the design of main modules in the receiver circuit are discussed in detail, including SDH and PDH interface module, SDH framer module, section overhead module in receiver, AU pointer interpretation module, high path overhead module, TU pointer interpretation module, low path overhead module, PDH processing module, payload analyzing module, MPI configure module, data comprehensive-processing module etc. Frame alignment design theory in SDH header module is fully demonstrated and the design method of frame synchronization state machine is given; meanwhile, descrambling code technology in SDH framer module is also analyzed in detail and computation method of 64-bit parallel scrambling data is extrapolated; then generation method of pseudo-random binary sequence (PRBS) in payback analyzing module is deducted, and a practical PRBS computation method is also given.RTL simulations were issued on the designed SDH network analyzer receiver circuit, and then FPGA implementation and board-level debug were issued on functional verified RTL design. The results of RTL simulations and board-level debugs prove that the presented design in this paper completely meet the demands of ITU-T and related domestic standards.The designed receiver circuit combines with transmitter circuit and other peripheral circuits, forming a SDH test instrument which is already put into market.