The Design Of The AOS Frame Synchronization Card Based On PCI Bus

In this thesis, the theory of synchronization, frame synchronization algorithm of AOS, the standards of PCI bus and the technologies of FPGA are studied deeply by designing frame synchronization card that is applied to AOS system.Synchronization has played more and more a role in the communication system. Synchronization technology is widely used in digital communications. In this thesis, on the basis of the synchronization algorithms, implementing paths and relative technologies developed in these fields, the frame synchronization system of AOS is implemented with FPGA.Due to its excellent performance such as bandwidth of the data, power dissipation, noise immunity and opening property, PCI bus wins rapidly increasing popularization and extensive application in the embedded system and the industrial control system. Have studied and analysed PCI bus standard deeply, the PCI bus controller is implemented with FPGA.Several aspects are included in the thesis:1)Analysing deeply the theory of synchronization and studying deeply the algorithm of frame synchronization.2)Several basis cells, such as frame head recgnization,shift,divider and protect in the frame synchronization system of AOS, are researched. On this basis, simulation is implemented.3)The frame synchronization system of AOS is implemented by using the basis cell which is mentioned above.4)Research and analyse deeply the PCI bus standard.5)The top-down design methodology is used to realize the PCI bus controller. This controller has four modules, such as Pcislave, DMA, Pargen, and Fifoct.6)The frame synchronization system of AOS is downloaded into the FPGA-PCI developboard and the result is validated. All modules are described in VHDL, simulated in Quartus 4.2, integrated into one and downloaded into the device EP1C12Q240C8. Tests indicate the frame synchronization card is successful.