Design Of Vehicle Fault Detection System Based On

Due to the rapid development of auto industry and the people in the process ofdriving safety requirements have become higher, and the use of the electronic device inthe car, the car driving become more comfortable and safe, so the car is also have moreand more the number of ECU, the subsequent also led to the car in the process ofvehicle electronic control unit failure probability, combined with the traditional car bodywiring way already cannot satisfy the various of requirements, so this article wasproposed based on FPGA and CAN bus technology to realize the design of auto faultdetection system.The main content of this thesis is a part of the main is realized on FPGA, includingusing Verilog language realization of CAN bus controller, fault detection module、SDRAM module、realize the whole communication system of one of the nodes and thefunction of data processing. Experimental plate as the other part is CAN buscommunication system of another node, the two parts by the bus transceiver connectedform a complete system of communication. Using Nios II core as the processor, theCAN bus through the Avalon bus controller and other hardware control, completed theconstruction of the fault detection communication system. Thesis mainly on bodytemperature and engine idle speed fault detection for validation, make body ECU datacan be transmitted through the CAN bus network, the user can know about the safety ofthe car at any time.