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A Design Scheme Of Digital Camera Based On SOPC

Posted on:2006-04-29Degree:MasterType:Thesis
Country:ChinaCandidate:J W SuFull Text:PDF
GTID:2132360155972476Subject:Instrument Science and Technology
Abstract/Summary:PDF Full Text Request
This paper as a part of the project "The research of the digital camera and the key technology"as the major project of information industry bureau of Chongqing, is focused on the integration of digital camera to implement a digital camera system having the function of picture capturing, saving, processing and so on. At first, this paper introduce the composition of the whole digital camera system and gives a brief introduction of its partial function and the relationship among them, establishes the scheme that based on the NIOS II which is one technology of SOPC of Altera and pulsing the Digital Signal Processor (DSP) as arithmetic unit. The following two parts is the central content of this paper that is the hardware design and software design parts. In the system, the hardware is mainly made of processor DSP (TMS320VC5416), coprocessor FPGA (EP1C6Q240) and some relevant components and sensors. The software consists of following parts: 1. the program of DSP that implements the function of coding and decoding of picture. 2. the program of NIOS II is used to gather the high-speed data and save it, and some interface function of SDRAM controller. Generally, the main task is collecting some document of CCD sensor, programmable chip EP1C6 and NIOS II, SDRAM, and designs the circuit board of the whole system. then debugging and testing the each module. This paper designs the PCB of front sensor CCD and program its registers. SDRAM is as buffer of capturing data, which is implemented by NIOS II. The data between NIOS II and DSP communicates through a high-speed SRAM to implement the coprocessing. DSP compresses the data of NIOS II, which is sent to CF card to save, or in another way, be sent to PC. At meanwhile, the data of CCD is also sent into buffer, which is displaying in the LCD controlled by FPGA. The system has strong expansibility and flexibility because of the architecture of basing on NIOS II and pulsing the DSP. The NIOS II is responsible for the high-speed interface and data transmitting, the DSP is in charge of system management and software coding. NIOS II is a soft core, which is in favor of designing special imbedded system. The more and more IP and support offering by the third person will upgrade the generality of the NIOS II system, which makes us possible to develop a good performance digital camera system with little money in a short time. The hardware system in this scheme has been verfied by PCB processing and function debugging.
Keywords/Search Tags:NIOS II, SOPC, DSP, CCD
PDF Full Text Request
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