The FPGA Design Of AOS Frame Synchronous Transmitter Based On PCI Bus

This paper mainly describes the design and implementation of AOSFrame Synchronous Transmitter based on the PCI Bus, and deeply analyses andresearches the frame synchronous communication technology, FPGA technologyand PCI bus standards.Frame synchronous transmitter works on the AOS physics layer。Itsfunction is adding the 4 bytes synchronous code 1ACFFC1D which is regulatedby CCSDS to the VC-PDU. This is PCA-PDU. Then send the data out serially.This design completes the Frame Synchronous transmitter using FPGA,including: 1)The theoretic research of frame synchronous transmitter; 2)Designthe basic modules: empty frame fill-in,FIFO,bit synchronous generation,parallel-to-serial transition,BUSMUX,frequency divider; 3)Put emphasis onthe FIFO,empty frame fill-in,gray code counter and bit synchronous generationmodules; 4) Synthesize all the above basic modules together and complete thetheoretic design of frame synchronous transmitter; 5)Research and analyze thePCI bus standard; 6)Design the basic modules of PCI bus controller, including:command and address decode and address counter,parity bit generation,paritybit check,configure space register and state controller of target device; 7)Research the simple application software on the basis of the driver and testprogram bringing with the development board.All modules are described in QUARTUSII using VHDL, integrated intoone chip and downloaded into the device EP1C12Q240C8. Tests indicate thatthe design is totally successful.