Application Of The Distributed Central Timing Trigger System On The EAST Superconductive Tokamak

EAST (HT-7U), established all by the Institute of Plasma Physics, the Chinese Academy of Sciences, is the first entirely superconductive Tokamak installation with non-round section all over the world, which is used to study the process of controlled nuclear fusion. This large-scale experiment equipment is involved with lots of discipline domains and engineering systems. On the whole, EAST is composed of many subsystems such as low temperature system, vacuum system, pole-orientation field, longitudinal field, rapidly controllable power source, microwave system, collecting system, diagnosing system and so on. The whole control system of EAST is a large distributed control system (It's distributed in the aspects of both physics and regions). Its one important constituent is named Central Timing Trigger system, which mainly supplies a control mechanism to send a series of trigger signals to start up every subsystem synchronous in the experimental process. Sequentially the Central Timing Trigger system can harmonize each subsystem and make them work according to the experimental working model fixed by central control system. At the same time, the Central Timing Trigger system gives all data collecting subsystems a uniform central clock to ensure good synchronization of the collected signals.This paper, first at all, has introduced the formation of the distributed Central Timing Trigger system of EAST. Then according to the experimental requirement of EAST, it has completed two designs, one of which is about the core module which can supply system clock and system trigger to each distributed node and the other is about circuits in every distributed node such as Ethernet interface circuit, clock frequency division and trigger delay module, photo-electricity switching circuit as well as periphery isolated drive circuit. The Ethernet interface circuit is based on AVR microcontroller ATmega128 and embedded RTOS Nut/OS to accomplish its main design. The clock frequency division and trigger delay module is introduced programmable logic device FPGA as its kernel device. Therefore the distributed central timing trigger system can output clock signals divided by any integer from 0 to 65535 with 32MHz input clock, it also can output trigger signals under 1 microsecond accuracy with the longest delay interval of 4294 second.The distributed Central Timing Trigger system has been applied to the discharge experiment with EAST. It's indicated that for a long time, this system with strong stability is easy to promote and transform to satisfy the experimental requirement ofEAST.