PWM Regulating Speed System Of DC Motor Based On Nios Ⅱ

Direct current motor has the characters of rapid response, high precision, great efficiency, heavy load ability and excellent controlling performance,and is used in various closed loop and half-closed loop control systems. With the development of EDA technology digital gate array FPGA presents a novel motor control system based on field programmable effective strategy.In this thesis Altera DE2 board is adopted as the integrated development platform, using SOPC technology to embed soft-core NiosII in the FPGA as central control device, to control the entire peripheral circuits with the help of Avalon bus so as to drive the motor running successfully.This methed is a different way from traditional motor control (that is,DC motor based on SCM or DSP).The software and hardware design of the system are presented in the thesis. For the hardware design program,first an overall design of the whole system is presented, then the design of each functional module, i.e. FPGA design, SDRAM and FLASH design, PWM module, speed detection module, clock source and keyboard interface circuit, is discussed in detail.Both of them use VHDL code to generate the interface functional module. As for the software design, an overall design of the whole system is presented, followed by each functional module's design flow. Motor control algorithms include incremental PID control algorithm and predictive functional control algorithm. The DC motor speed control software is programmed with C code into the Nios II IDE. The electrical parameters are identified from the principle model, and finally the experimental results of the overall speed control system are discussed.