EPIC Architecture Study And Pipeline Implementation

This project is the preparation for the 64-bit general purpose high-performance microprocessor chip design "863" significant prjoect. Research and analysis are made detailed on EPIC based microprocessor. EPIC architecture tight combine hardware and software to improve performance. The design of branch prediction is mainly studied and the integer pipeline of processor based on EPIC architecture is designed and realized in this paper.First, EPIC architecture is analyzed and its speculation technique and predicated execution technique are thoroughly studied. Then multi-level branch prediction in the front end is analyzed carefully and each-level predictor is implemented on the basis of Itanium processor which is a commercial EPIC processor. Through multi-level prediction strategy, prediction precision and processor performance are enhanced. In addition, it is developed that an integer pipelining design and implementation of high-performance processor based on EPIC architecture. In this design, register stack mechanism and register rotation mechanism in design is studied and instruction dispatch and instruction rotation function are achieved. At the same time, the strategy of register rename and designing integer units are put forward and some special integer instructions are disposed and optimized specially. Finally, it is given that the result of simulation and validation for the whole integer pipeline.