| When the process of very large-scale integrated circuits (VLSI) is scaling down into deep sub-micron, the complexity of the design has increased. Testing of a chip, has posed some challenges. Logic Built-In Self-Test (LBIST) has been widely accepted as an effective DFT technique for VLSI and SOC designs, among many kinds of proposed design for testability (DFT) techniques to improve testability of chip.This dissertation conducts researches on the application of different DFT techniques, discuss key problems in practical application of LBIST. On this basis, a new deterministic and low power pattern generation structure is presented to address the power problem.The contributions of the dissertation are listed as followings:1. The advanced DFT techniques of general-purposed CPU chip. We analyze the different DFT techniques in industry, and apply them in a high-performance general-purposed CPU chip, including internal scan design, built-in self-test, and boundary scan design. Experimental results show our design obtains relatively high fault coverage.2. Research on key techniques in BIST implementation for logic cores. As an important technology of DFT, LBIST has been paid more and more attention in resent years. We analyze some key problems in practical application of LBIST, and apply the solutions in a general-purposed CPU chip. Experimental results show LBIST can get high fault coverage with low area and performance overhead.3. A deterministic and low power LBIST method is provided. LFSR reseeding is a very powerful deterministic LBIST method for test data compression, but the decoding course of LFSR can cause high power dissipation. We analyze various kinds of deterministic pattern generation methods. On this basis, we present a new deterministic and low power pattern generator structure used in conjunction with LFSR reseeding. The proposed scheme utilizes scan slices overlapping of test patterns to reduce the number of specified bits and the number of transitions at the same time. A decoder is used to generate control signals. Experimental results indicate that the proposed method significantly reduces the switching activity by 80% and only needs a relatively small (25% of the original Mintest test sets) test data storage. Therefore, the proposed scheme results in a good tradeoff between test data compression and test power reduction compared with other existing methods. And, it can result in even better result if it is combined with other LBIST techniques such as partial reseeding or seed compression. |
