Design And Implementation Of A MC68HC08 Compatible MCU IP Core

This paper presents the design and verification of 8-bit MCU(Micro Controller Units) SD-HC08 IP core based micro processor, which is compatible with the instruction set of Motorola68HC08. SD-HC08 uses the rich and high efficient instruction set to reduce the required program memory, compared to RISC (reduced instruction set computer) product.This design adopts the top-down methodology and describes the system architecture analysis, sub-modules division and design, logic synthesis, functional simulation and verification. EDA tools from Synopsys and Cadence are used during different design periods.During the RTL design level, this design describes each sub-module using Verilog HDL language, and then simulates these modules and the whole system using Cadence NC-Verilog.During the verification period, we consider Freescale HC08 Codewarrior IDE as a reference model. The system is validated by the method of direct test, with the combination of random test. Random test is realized by generating single instruction randomly, which is necessary to ensure complete verification.According to the characteristic of SD-HC08 system, proper synthesis strategy and optimization methodology is adopted to synthesize the IP core with Synopsys's Design Compiler. The synthesis result is analyzed in this paper.We design the simplest circuit and share the resources to save the system resources, without affecting the circuit function. SD-HC08, which is widely used in the application of low power and high ratio of performance to price control system, is fully compatible with MC68HC08. This thesis accumulates valued experience for the future development of large scale micro processor.