Built-in Self-test Design Of Embedded SRAM

With the deep sub-micron process technology development, today's chips contain more embedded SRAM. Embedded SRAM test has become an important research topic. However, as memory is embedded in the chip, not all pins are connected to the pin on the chip, the traditional testing plan could not effectively support the test, and built-in self-test (BIST) for embedded memory becomes an economic and effective way for currently testing.This paper is designed for the BIST which aims at a Test_chip of 4 K×8bit dual-port SRAM. It has first analyzed SRAM logic errors, fault model; Then researched the relevant test algorithm and used MARCH C + and MARCH d2pf algorithms, which MARCH C + algorithm is extended the word-oriented algorithm. These combination of the use of two algorithms increase fault coverage; The Sequential design uses a parallel processing approach, because theoretical analysis shows that the approach can reduce the testing time effectively; BIST module design is used RTL code which based on the verilog language and increased a built-in self-test (BISA) module in the traditional BIST modules, which will transmit the fault information to the serial form of output, to reduce the difficulty of chip debug; Finally uses FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.