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The Design Of Image Signals And Data Signals Access To Image Processing System Based On FPGA

Posted on:2011-03-01Degree:MasterType:Thesis
Country:ChinaCandidate:S Y WangFull Text:PDF
GTID:2178360305460292Subject:Pattern Recognition and Intelligent Systems
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With the high-speed development of computer, multimedia and data communication technology, image processing technology has been widely used in various areas. The design of the external interface module has been proposed in the background of the high-speed, high-performance image processing hardware platform based on DSP and FPGA. The external interface module includes an external interface board and an internal PCI board. Different kinds of interfaces outside the system are accessed by the external interface board. The outside signals are accessed to the image processing core system by the internal PCI board. The signals are connected by the LVDS signal between the external interface board and the internal PCI board.The main works of this dissertation are summarized as follows:1. The external interface board has been designed in this dissertation, so that different kinds of data signals and image signals can be accessed to the image processing system.2. In the environment of Xilinx ISE 9.2i, the UART has been designed based on the FPGA Virtex-4 chip XC4VFX60, then 8-channel RS-232 signals and 16-channel RS-422 signals can be accessed to the system by the UART. The emphasis is the design of the UART baud generation module, the UART receiver module, data buffer module, the UART send module.3. Because there are not enough 10 pins, the multi-channel TDM has been designed.8-channel RS-232 signals and 16-RS422 signals can be respectively changed to one-channel LVDS signal by the module TDM. Then the LVDS signal can be accessed to the image processing system.The function of 8-channel RS-232 signals and 16-channel RS-422 signals's access and multi-channel TDM is simulated in the ISE Xilinx 9.2i by ISE Simulator. The results show that the multi-channel signals can be accessed by UART correctly and can be changed into one-channel LVDS signal according to the requirements.
Keywords/Search Tags:Image Processing, Serial Communication, FPGA, UART, TDM
PDF Full Text Request
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