Based On Fpga Digital Phase Meter

According to the special requirements in the practical project, a way of digital phase detector is studied in this thesis, which is based on FPGA and FFT algorithm. The thesis that begins with theory of phase detection and analyses the shortcomings of traditional phase detector demonstrates a highly reliable phase detection algorithm. Furthermore, by using FFT and analyzing the spectrum, we implement the phase-detcting of reference signal and measurement signal. Meanwhile, the thesis expounds the advantages of FPGA in realization of FFT algorithm.In the course of FFT realization based on FPGA, the thesis profoundly studies the character of FFT algorithm and detailedly analyses the hardware structural traits of algorithm implementation .In the meantime, it deeply optimizes the hardware structure. In the optimized hardware structure, many multipliers parallel computation is adopted to accelerate the computing speed of butterfly. In addition, dual-RAM and twiddling-factor ROM are built inside the system to enhance the speed of data transformation. Meanwhile the pipeline pattern is used to coincide the data computation with the data access. In the design, VHSIC Hardware Description Language (VHDL) is used to describe the circuit. With the help of the Quartus II software of Altera, the design offers the simulation result.The simulation results shows that FFT phase-detecting algorithm based on FPGA meets the needs of phase detection regardless of speed and precision. Moreover, its computing 64-point data only needs 27.5 μs and the most error is within 1%. Therefore, FPGA is used as an innovation chip which owns fast speed, high reconfigurability, as well as short development period and takes up an important position in the future design of electronic system.