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Design Of A PLL Circuit Applied To Synchronous DC/DC Converter

Posted on:2015-08-15Degree:MasterType:Thesis
Country:ChinaCandidate:Q Y ZhangFull Text:PDF
GTID:2272330473952885Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Along with the rapid development of Power Management technology, DC/DC converter has been well used in communication, computer, LED drive, etc. And it requires different characteristics under different applications. DC/DC converters with synchronic function can be used in multiphase control system, which can develop the driving ability. It is very suitable for distributed power management system.When working in sync mode, a DC/DC converter can receive a clock input signal from an external pin. The external clock mostly has a good long-term stability, but its noise and jitter is too large. In order to overcome this problem, this paper proposes a 3-order charge-pump phase-locked loop (PLL). Taking its advantages of good short-term stability, small noise and jitter, we can stabilize the input clock signal. And we can realize the synchronization of the output switching point and the input clock when the proposed circuit is put into the control loop of the DC/DC converter.Starting with the principle, structure and the working principle of phase-locked loop, this paper introduces the charge-pump phase-locked loop in detail and researches its linear model, loop stability and dynamic characteristics. Based on these theories, this paper proposes a 3-order charge-pump phase-locked loop. It is consisted of digital phase and frequency detector (PFD), symmetric charge-pump, bandgap, loop filter, voltage-controlled oscillator (VCO) and so on. At last, combined with the theory of valley current mode DC/DC converter, we use the proposed PLL to control the DC/DC converter working in synchronous mode.Using CSMC 0.25μm BCD process, we verify the proposed PLL with Hspice simulator. The result indicates that the PLL can realize phase lock at the input range of 200 kHz-2MHz@5-5.3V supply voltage. In typical case, its lock-time is less than 75μs, jitter of cycle is less than 5ns, and the whole power consumption is lower than 903μW. Besides, we verify its ability to control the DC/DC converter working in synchronous mode. And the simulation results show that the proposed PPL circuit realizes the expected function.
Keywords/Search Tags:Phase-locked Loop, Charge-pump, VCO, Sync mode, DC/DC converter
PDF Full Text Request
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