A Low-quiescent-current Capacitor-less LDO Using An Adaptive PSR Optimization Technique

With the continuous development of integrated circuit technology,the reduction of transistor size has increased the integration density of the chip and circuit functions,making power management circuits more complicated.Voltage regulators are key components for power management,as they provide a regulated,stable and noise-free supply voltage to the active blocks of an So C.LDO(Low Dropout Regulator)is a kind of voltage regulator,which has better immunity to power supply noise than switched-capacitor regulator or switching regulator.Generally,in order to obtain better transient response and stability,a large capacitance(μF)will be loaded at the output of the LDO.However,in recent years,researches on CL-LDO(Capacitor-less LDO)have become a trend to improving the integration of LDOs.But CL-LDO has more severe stability problems,as well as worse transient response and power supply rejection(PSR).To improve the PSR of CL-LDO,this paper proposes an adaptive optimization technique for PSR with low quiescent current,that is,injecting an adjustable frequency-dependent compensation current into the gate of the pass transistor.Using a push-pull amplifier as the feedback amplifier avoids complex frequency compensation circuits and a bulky external capacitor,thereby reducing the area.Secondly,a differential symmetrical current amplifier without large resistance is used in the PSR enhancer to reduce the DC offset and area.Moreover,a traditional scaled replica of the pass transistor is not used in PSR enhancer.Instead,the MOS compensation capacitor is dynamically adjusted by sensing the working state of the pass transistor,which further reduces the quiescent current.For the voltage reference,based on the basic differential pair of the resistor-less bandgap reference,a resistor-less high-order temperature compensation technique is proposed,that is,biasing currents with the same temperature coefficient for bipolar transistors of different specifications,and using differential pairs to extract high-order temperature term in the emitter-base voltage of PNP,and then eliminating high-order term through the weighted summation circuit.The current source is exponentially related to the temperature and has a negative feedback loop to reduce the channel length.At the same time,two identical PMOS transistors working in the subthreshold region are connected in series to divide the emitter-base voltage.The temperature compensation circuit realizes the weighted value by stacking up multiple differential circuits to reduce the circuit noise.The bandgap and CL-LDO are based on HGrace 0.11μm CMOS process for circuit design and simulation,with areas of 0.013 mm~2and 0.026 mm~2,respectively.The post-simulation results of the bandgap show that the supply voltage is 2-3.3V,and the output reference voltage is 0.612V.The optimal TC is 0.8/℃,and the maximum quiescent current is 34μA.The tape-out experimental results of the CL-LDO show that the input voltage is 2-3.3V and the output voltage is 1.8V.The maximum quiescent current is55μA with 0.1m A-80m A load current.In the frequency range of 8k Hz to 1MHz,the maximum PSR improvement is 21d B～37d B with different dropout voltages and load currents.