Single-stage The The Apfc Chip Design,

By entering the twenty-first century, the PFC technology is rising fast all over the world, especially in our country. Improving the power factor are needed in the regard of requirements and standards. Improve the power factor can reduce the input current harmonic components, thereby reducing interference to other equipment. Improve the power factor is one of the important means to save energy, to improve power quality by ensuring safe and stable operation of the power system. Electrical equipment used in the PFC to improve power factor, can increase efficiency and reduce machine power supply costs, increase reliability, to improve the competitiveness of their products is very important.The Power factor, harmonic current and the inductor size and the structure of the circuit topology is closely related to each other, this is the real motives of researching a single-stage FPC in recent years. Single-stage PFC technology is still an upward trend, the reasons have not yet reached its optimal performance, many problems remain to be further resolved, the analysis and design of a lot of work to be done, and to make an objective comparison between Single-stage PFC and two-stage PFC are needed.This paper designed a single-stage APFC chip, from introduce the operation principle and working way of the APFC, conceive out the overall function of the circuit diagram, then complete each module of the circuit design and simulation, as well as the territory of the design and verification. Finally, create the model of the outside circuit, complete the the simulationof the entire circuit systemly.This circuit was designed by using the Cadence EDA software, and using Calibre software to verify DRC and LVS. The craft adopts CSMC 0.5um N-WELL CMOS DPTM craft technology.