Ddr2 Sdram High-end Digital Storage Oscilloscope

More and more high storage requirements come out along with the continuous improvement of sampling rate in the data acquisition and storage systems. The development in the modern testing field incline to High-speed sampling and large-capacity storage which also have already widely been used in digital storage oscilloscopes, logic analyzers and other test instruments. The high-speed and large-capacity data storage systems introduced in this thesis focus on the application demand of high-side digital storage oscilloscope, also, the core and difficult module of the entire system.With the enhance of integration process and the improvement of ADC architecture, the maximum sampling rate of Analog-to-Digital Converter chip has reached GSPS-class, together with the improvement of Parallel Sampling technology, most requirements of the data acquisition system could be fulfilled. But that needs high-speed data memory to match. At the same time, high-speed sampling rate would bring huge data flow, therefore, large capacity memory as a sampled-data cache is usually required.Based on the analysis of high-end digital storage oscilloscope system performance requirements and the data throughput requirements of data acquisition front-side, the high-speed & large-capacity storage system program built in this thesis, using second-generation double data rate memory DDR2 SDRAM to realize high-speed mass data cache. Simultaneously, combined with trigger control, the work described in the thesis deepens the effective depth of data storage.Storage controller module implements 3GByte/s storage speed and 128Mpts continuous storage capability through the design of DDR2 SDRAM controller. The main control logic of DDR2 memory, clock management, addressing mode and the implementation of trigger function under long storage mode are analyzed in detail in the thesis. According to the refresh characteristic of Dynamic Random Access Memory, the design uses asynchronous FIFO to achieve the data transfer through ADC, DDR2 memory chips and DSP clock domain. And solve the problem of responding slowly in the digital storage oscilloscope of deep-memory by presenting a method of rapid positioning and scaling technology.