Large Capacity Storage And Processing Technology For High Speed And High Precision Sampled Data

A large-capacity storage and processing system for high speed and high precision sampling data,under the condition of oscilloscope acquisition system with high sampling rate and high resolution,is studied and designed in this paper.In this project,the oscilloscope design indicators are: dual-channel 20 GSPS or four-channel 10 GSPS realtime sampling rate,10 bit vertical resolution,1Gpts storage depth,and maximum storage number 65536 in segmented storage mode.The specific research contents of this paper mainly include:First,the hardware architecture and acquisition principle of the ultra-high speed parallel acquisition system are studied and analyzed.According to the throughput of the data output of the acquisition system,the throughput of the storage system requirements are calculated,and the overall architecture of the storage system is designed.A storage architecture consisting of 8 synchronous dynamic random access memory(SDRAM)memory modules and 8 SDRAM memory chips is designed to store high speed and high precision sampled data in a high speed parallel acquisition system.Second,under the designed storage framework,the logic implementation of single ADC high-precision sampling data storage is designed.The parallel storage of one SDRAM memory module and one SDRAM storage chip improves the receiving capacity of the storage system for the sampled data of a single ADC,so as to realize the integrity storage of the high-precision sampled data of a single ADC by the storage system.Third,in the design of the storage framework,the logic implementation of multiple ADC sampling data storage synchronization is designed.It includes design of storage synchronization of multiple ADC sampling data in multi-memory,design of suspended synchronization of segmented storage mode under multi-adc sampling data.Fourth.Under the designed storage framework,the processing system of high-speed and high-precision sampling data is designed.It includes synchronous processing of single memory module and single storage chip read data under single ADC single FPGA,synchronous processing of multiple memory modules and chips read data under multiple ADC multiple FPGA,and peak sampling processing of large amount of data stored to read.Through the simulation,debugging and functional testing of each functional module,this paper realizes the design of the storage depth of 1Gpts under 20 GSPS sampling rate and 10 bit vertical resolution,and realizes the design of the maximum storage of 65,536 waveforms under the segmented storage mode,reaching the project design indicators.