Ldos Low Dropout Linear Regulator Design

A low quiescent current LDO is presented in this thesis,which is designed and simulated based on SMIC 0.18um Logic CMOS process.By using an improved current reference,and optimizing the resistor feedback network,the quiescent current is effectively reduced.The simulation results show that the maximum quiescent current is 27.39uA and 38.33uA when circuit is in standby mode and in normal work mode respectively.The line regulation and load regulation is less than 0.22mV/V and 1.6%respectively in typical condition.The maximum load current is 150mA,and the dropout voltage is 250mV when output current is150mA.