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Research Of Portable Fault Recorder Based On Fpga

Posted on:2011-02-12Degree:MasterType:Thesis
Country:ChinaCandidate:T F YuanFull Text:PDF
GTID:2192360305988668Subject:Power electronics and electric drive
Abstract/Summary:PDF Full Text Request
With the demand of the electricity of the people, power system is developing toward the sophisticated, widespread and intelligent direction. Therefore, the analysis of fault with the power system is increasingly important. As the essential technology of the power system fault analysis, fault recording technology has made significant. development in the developing process of the power system. However, some insufficiency still exists in the traditional fault recorder, such as insufficient sampling rate and low accuracy, so that the traditional fault recorder can't meet the needs of the current power system fault already. At the same time, although fault recorder has greatly improved its performance by the introduction of new technology, but it is also brought a lot of problems such as poor stability and the lack of a reasonable configuration and other issues. Therefore, it is important that to improve the stability and the rationality of allocation of the device in the premise of performance of the fault recorder.This paper established a new type fault recorder based FPGA which met the requirements of data collection,in allusion to the lack of traditional fault recorder. The system carried out a system with high-speed and high-precision data acquisition and transmission based on FPGA through the expanded of the data acquisition circuit, human-computer interaction and communication circuit. This paper built a digital signal processing module in the FPGA by using the DSP Builder tool.It achieved the functions of digital filtering and fast Fourier transform which is in order to achieve the frequency domain analysis of fault data. At the same time, digital signal processing module also completed a start criterion algorithm, to protect the reliability of the device starts. The paper built a soft core processor which named NIOS II in the FPGA by using SOPC technology, and runningμC/OS-Ⅱoperating system on the NIOS II soft-core in order to achieve the scheduling of the system task. Through the simulation and actual test, this system can complete fault signal acquisition and storage functions.Therefore, this device is applied to the recorded task of the power system fault signals in the new time.
Keywords/Search Tags:Fault recorder, FPGA, DSP Builder, NIOS II
PDF Full Text Request
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