Study On Low-power Dwt Architecture And Hardware Implementation For Jpeg2000

As the latest still image compression international standard, JPEG2000 adopts Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT), which achieves much better coding efficiency and image quality than the traditional methods. With its excellent performance and prominent features, JPEG2000 will no doubt become the main-stream in the image compression field in the future. Therefore, high attention is paid to Lifting-based DWT, which is adopted by JPEG2000 as its key technology. It is a challenge to design VLSI architecture for wavelet implementation with real-time, low area and power consumption.According to the requirement of hardware design, this dissertation proposes a new VLSI architecture design of 2D-lifting wavelet transform, which is suitable for dealing with the real-time image compression. The whole architecture is optimized in pipeline design way which increases the operation speed. Adopt time division multiplex (TDM) design, which reduces the size of the circuit. Adopt shift-add operations to substitute multiplications, and adopt multiplexer to realize the embedded extension algorithm, which reduce the operation amount. Finally, the architecture is described by Verilog HDL in register transfer level (RTL). The synthesis, simulation and on-line debugging of this design are implemented with the assistance of EDA tools. And the result of simulation and synthesis is given out. The results illustrate that the architecture possesses strong processing ability and low power consumption in real time image processing and creates good condition for coding and transmission.This dissertation successfully accomplished the design of low-power and high-speed 2D DWT architecture. It has built a solid foundation for the future study of JPEG2000 image compression system.