Dwt Coding And Tier1 Encoding. Jpeg2000 Vlsi Design And Realization

Digital images have been used widely in modern society nowadays. Because of the huge size of the raw image format, much importance has been attached to the JPEG2000. Although JPEG2000 has been determined at the end of 2000, the technology can not be recognized in computer networks, wireless communications and other practical applications. Its function has to be further strengthened. Standards adopt the Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT), which include a large number of time-consuming and complex algorithms, therefore new requirements are needed in order to improve the encoding speed and meet the real-time applications.This paper researches on the first part of JPEG2000 standard, analyses the JPEG2000 coding system for each coding module, study and optimize the core algorithm of discrete wavelet transform, bit plane coding and arithmetic coding. In real-time image coding system, the wavelet transform as a result of the calculation of a larger volume requires a large amount of storage space. It is not conducive to high-speed and low power requirements of the hardware implementation. So the hardware architecture of two-dimensional 5/3 wavelet transform based on a pipelined processing is designed in this paper. The architecture adopted the periodic symmetric extending approach to restrain discontinuity of the edge of the signal and ensure the normal operation of the pipeline by adding the buffer module between row transform and column transform. The use of multiple data parallel input mode scheduling has greatly increased the processing speed of the module.EBCOT algorithm is the most complex one in the entire system of JPEG2000. The part of the processing time is usually more than 50% in the core of the JPEG2000 algorithm. Therefore, EBCOT algorithm becomes the difficulty of JPEG2000 compression system design. To solve this problem, the bit-plane encoder VLSI structure based on three parallel processing is designed, the way of encoding all the data in a bit-plane during a clock cycle is proposed which greatly enhanced the speed of the encoding. As for the VLSI implementation of binary arithmetic codec, the binary arithmetic codec based on three-pipeline architecture is presented, which reduces the coding complexity,assigns work process of each module and improve the encoding speed.The three proposed architecture is implemented by Verilog HDL at the end of the paper. The result of simulation and synthesis proves the correctness of the design.