Along with the development of market economy and improvement of people's standard of living, requirement of safeguard and locale recorder alarm system is larger and higher in fields such as bank, electrical power, traffic, safety, storage, building and military affairs establishment. Video surveillance system has outstanding features, including real time inspecting objects, support far distance transmit and convenient for manager to control, so it attaches people's great importance increasingly.Companies always adapt the ways using CPU+DSP to implement the monitor system. This realization has high cost and poor agility, but using programmable logic device can recuperate these defects. The function of the original CPU+CPLD combination can be realized by one FPGA chip. It needs to realize a 32-bit Nios II CPU adding with the hardware logic of video signals select, storage and color space transform in a FPGA chip. The SOPC technology which creates programmable system on a single chip is on the edge of this field.The research content has mainly the following several aspects:1. The block diagram of embedded camera control system based on NiosII and the architecture of its core controller.2. The research of making an IP core with Verilog HDL and making an IPcore named Camera_show which can perform the functions including video signals select, assign, storage and color space transform .3. The technologies of SOPC, Designing a 32 bits Nios II CPU with SOPC.Create a SOPC by linking periphery control logic and user logic with Avalon Bus.4. The software design of USB communication.The EP2C35F627C6 chip of Altera Corporation's Cyclone II family is used in this design. The system of Nios II CPU . Camera_show IP core and periphery control logic composition is designed with SOPC. This system designed by the Top to bottom mode.To implement the user logic part of the system, it can use modularize design measures. Firstly, divide the Camera_show IP core into several... |